N74F166N,602 NXP Semiconductors, N74F166N,602 Datasheet - Page 2

• Manufacturer Part Number: N74F166N,602
• Description: IC SHIFT REGISTER 8BIT 16-DIP
• Manufacturer: NXP Semiconductors
• Series: 74Fr

Specifications of N74F166N,602

• Package / Case: 16-DIP (0.300", 7.62mm)
• Logic Type: Register, Bidirectional
• Function: Universal
• Output Type: Standard
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Counting Sequence: Serial/Parallel to Serial
• Number Of Circuits: 1
• Logic Family: F
• Propagation Delay Time: 7.5 ns
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Supply Voltage (min): 4.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3167-5; 933794760602; N74F166N

Philips Semiconductors
FEATURES
DESCRIPTION
The 74F166 is a high speed 8–bit shift register that has fully
synchronous serial parallel data entry selected by an active
low parallel enable (PE) input. When the PE is low one setup
time before the low–to–high clock transition, parallel data is
entered into the register.
When PE is high, data is entered into internal bit position Q0
from serial data input (Ds), and the remaining bits are shifted
one place to the right (Q0
positive going clock transition.
ORDERING INFORMATION
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
Note to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20 A in the high state and 0.6mA in the low state.
Feb. 14, 1991
High impedance NPN base inputs for reduced loading
(20 A in high and low states)
Synchronous parallel to serial applications
Synchronous serial data input for easy expansion
Clock enable for ”do nothing” mode
Asynchronous master reset
Expandable to 16 bits in 8–bit increments
Industrial temperature range available (–40 C to +85 C)
8-bit bidirectional universal shift register
16–pin plastic DIP
16–pin plastic SO
DESCRIPTION
D0 – D7
PINS
MR
CP
CE
PE
Q7
Ds
Parallel data inputs
Serial data input (shift right)
Clock input (active rising edge)
Clock enable input (active low)
Parallel enable input (active low)
Master reset input (active low)
Data output
COMMERCIAL RANGE
T
Q1
amb
V
CC
N74F166N
N74F166D
= 0 C to +70 C
= 5V 10%,
Q2, etc.) with each
DESCRIPTION
ORDER CODE
2
For expansion of the register in parallel to serial converters,
the Q7 output is connected to the Ds input of the succeeding
one input to be used as an active–low clock enable (CE)
input. The pin assignment for the CP and CE inputs is
arbitrary and can be reversed for layout convenience. The
low–to–high transition of CE input should only take place
while the CP is high for predictable operation. A low on the
master reset (MR) input overrides all other inputs and clears
the register asynchronously, forcing all bit positions to a low
state.
stage. The clock input is gated OR structure which allows
74F166
T
INDUSTRIAL RANGE
amb
TYPE
V
CC
= –40 C to +85 C
I74F166N
I74F166D
= 5V 10%,
TYPICAL f
74F (U.L.) HIGH/
175MHz
1.0/0.033
2.0/0.066
1.0/0.033
1.0/0.033
1.0/0.033
2.0/0.066
50/33
LOW
max
TYPICAL SUPPLY CUR-
LOAD VALUE HIGH/
Product specification
RENT( TOTAL)
1.0mA/20mA
PKG DWG #
20 A/20 A
40 A/40 A
20 A/20 A
20 A/20 A
20 A/20 A
40 A/40 A
853–0349 01718
SOT109-1
50mA
SOT38-4
74F166
LOW