74LV164D,118 NXP Semiconductors, 74LV164D,118 Datasheet - Page 11
![IC 8BIT SHIFT REGISTER 14SOIC](/photos/6/57/65749/14-soic-sot108-1_sml.jpg)
74LV164D,118
Manufacturer Part Number
74LV164D,118
Description
IC 8BIT SHIFT REGISTER 14SOIC
Manufacturer
NXP Semiconductors
Series
74LVr
Datasheet
1.74LV164BQ115.pdf
(21 pages)
Specifications of 74LV164D,118
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Logic Type
Shift Register
Function
Serial to Parallel
Output Type
Standard
Number Of Elements
1
Number Of Bits Per Element
8
Voltage - Supply
1 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Counting Sequence
Serial to Parallel
Number Of Circuits
1
Logic Family
LV
Propagation Delay Time
12 ns
Supply Voltage (max)
5.5 V
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74LV164D-T
74LV164D-T
935067450118
74LV164D-T
935067450118
Philips Semiconductors
[2]
[3]
12. Waveforms
9397 750 14501
Product data sheet
C
P
f
f
C
V
N = number of inputs switching;
The condition is V
i
o
(C
D
CC
PD
= input frequency in MHz;
L
= output frequency in MHz;
= output load capacitance in pF;
= C
L
is used to determine the dynamic power dissipation (P
= supply voltage in V;
PD
V
CC
2
V
CC
f
o
2
) = sum of the outputs.
I
= GND to V
f
i
N + (C
Fig 6. Propagation delay clock (CP) to output (Qn), clock pulse width and maximum clock
Fig 7. Pulse width master reset (MR), propagation delay master reset (MR) to output (Qn)
L
CC
.
Measurement points are given in
V
frequency
Measurement points are given in
V
and removal time master reset (MR) to clock (CP)
V
OL
OL
CC
2
and V
and V
Qn output
f
MR input
CP input
o
) where:
OH
OH
Qn output
CP input
are typical output voltage drop that occur with the output load.
are typical output voltage drop that occur with the output load.
GND
GND
Rev. 03 — 4 February 2005
V
V
OH
OL
V
V
I
I
GND
V
V
OH
OL
V
D
I
in W).
Table
Table
V
t
PHL
M
t
W
9.
9.
V
V
M
M
1/f
max
t
PHL
8-bit serial-in/parallel-out shift register
t
W
V
M
t
PLH
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
t
rem
V
001aac426
M
001aac427
74LV164
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