AM29PDL129H AMD [Advanced Micro Devices], AM29PDL129H Datasheet - Page 11

• Manufacturer Part Number: AM29PDL129H
• Description: 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode Simultaneous Read/Write Flash Memory with Enhanced VersatileIO
• Manufacturer: AMD [Advanced Micro Devices]

DEVICE BUS OPERATIONS
Legend: L = Logic Low = V
A
Notes:
1. The sector protect and sector unprotect functions may also be implemented via programming equipment. .
2. WP#/ACC must be high when writing to sectors SA1-133, SA1-134, SA2-0, or SA2-1.
Random Read (Non-Page Read)
Address access time (t
stable addresses to valid output data. The chip enable
access time (t
dresses and stable CE# to valid data at the output in-
puts. The output enable access time is the delay from
the falling edge of the OE# to valid data at the output
inputs (assuming the addresses have been stable for
at least t
Page Mode Read
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read oper-
ation. This mode provides faster read access speed
for random locations within a page. Address bits A21–
A3 select an 8-word page, and address bits A2–A0 se-
lect a specific work within that page. This is an asyn-
chronous operation with the microprocessor supplying
the specific word location.
The random or initial page access is t
subsequent page read accesses (as long as the loca-
tions specified by the microprocessor fall within that
page) are t
serted (CE1#=CE2#=V
CE2# for subsequent access has access time of t
or t
OE# is the output control and should be used to gate
data to the output inputs if the device is selected. Fast
page mode accesses are obtained by keeping A21–
A3 constant and changing A2 to A0 to select the spe-
cific word within that page.
November 2, 2005
Read
Write
Standby
Output Disable
Reset
Temporary Sector Unprotect (High
Voltage)
IN
CE
= Address In, D
. Here again, CE1#/CE2# selects the device and
ACC
Operation
PACC
–t
OE
CE
. When CE1# and CE2# are deas-
time).
IN
) is the delay from the stable ad-
= Data In, D
ACC
IH
IL
), the reassertion of CE1# or
, H = Logic High = V
) is equal to the delay from
OUT
Table 1. Am29PDL129H Device Bus Operations
CE1#
0.3 V
V
H
H
IO
X
X
L
L
L
= Data Out
±
ACC
CE2#
V
0.3 V
IO
H
H
L
L
L
X
X
or t
IH
±
, V
CE
ID
Am29PDL129H
and
OE#
= 11.5–12.5 V, V
ACC
H
X
H
X
X
L
WE#
Simultaneous Operation
In addition to the conventional features (read, pro-
gram, erase-suspend read, and erase-suspend pro-
gram), the device is capable of reading data from one
bank of memory while a program or erase operation is
in progress in another bank of memory (simultaneous
operation), The bank can be selected by bank ad-
dresses (A21–A20) with zero latency.
The simultaneous operation can execute multi-func-
tion mode in the same bank.
H
X
H
X
X
L
HH
RESET#
V
0.3 V
= 8.5–9.5 V, X = Don’t Care, SA = Sector Address,
Word 0
Word 1
Word 2
Word 3
Word 4
Word 5
Word 6
Word 7
V
Word
IO
H
H
H
L
ID
±
Table 2. Page Select
WP#/ACC
(Note 2)
X
X
X
X
X
X
A2
0
0
0
0
1
1
1
1
Addresses
(A21–A0)
A
A
A
X
X
X
IN
IN
IN
A1
0
0
1
1
0
0
1
1
DQ15–
High-Z
High-Z
High-Z
D
DQ0
D
D
A0
OUT
0
1
0
1
0
1
0
1
IN
IN
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