AM29PDL129H AMD [Advanced Micro Devices], AM29PDL129H Datasheet - Page 35

• Manufacturer Part Number: AM29PDL129H
• Description: 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode Simultaneous Read/Write Flash Memory with Enhanced VersatileIO
• Manufacturer: AMD [Advanced Micro Devices]

AC CHARACTERISTICS
CE1#/CE2# Timing
Read-Only Operations
Notes:
1.
2. See
3. Valid CE1#/CE2# conditions: (CE1#= V
4. Valid CE1#/CE2# transitions: (CE1#= CE2#= V
November 2, 2005
JEDEC
JEDEC
t
t
t
t
t
t
t
GHQZ
AVQV
ELQV
GLQV
EHQZ
AXQX
AVAV
Not 100% tested.
V
CE2#=V
Parameter
Parameter
IH
, CE2#=V
Figure 8
CE1#
CE2#
IH
t
t
Std.
t
PACC
t
t
t
OEH
ACC
t
t
t
) or (CE1#= V
RC
OE
OH
CE
DF
DF
t
Std
CCR
IL
and
).
Figure 10. Timing Diagram for Alternating Between CE1# and CE2# Control
Description
Read Cycle Time (Note 1)
Address to Output Delay (Note 3)
Chip Enable to Output Delay (Note 4)
Page Access Time
Output Enable to Output Delay
Chip Enable to Output High Z (Notes 1, 5, 6)
Output Enable to Output High Z (Notes 1, 5)
Output Hold Time From Addresses, CE#/CE2#
or OE#, Whichever Occurs First (Notes 5, 6)
Output Enable Hold Time
(Note 1)
Table 16
CE1#/CE2# Recover Time
IH
, CE2#=V
for test specifications
IL
).
IL
, CE2#= V
IH
Description
) to (CE1#= V
Read
Toggle and
Data# Polling
IH
) or (CE1#=
Am29PDL129H
t
IL
CCR
,
5. Measurements performed by placing a 50 ohm termination on the
6. Valid CE1#/CE2# transitions: (CE1#= V
7. For 70 pF output load capacitance, 2 ns will be added to t
CE#, OE# = V
Test Setup
OE# = V
data pin with a bias of V
bus driven to V
V
t
PACC
IH
, CE2#=V
, t
Min
OE
IL
values for all speed options.
IL
IL
) to (CE1#= CE2#= V
CC
Max
Max
Max
Max
Max
Max
/2 is taken as t
Min
Min
Min
Min
t
CCR
CC
All Speed Options
/2. The time from OE# high to the data
53
55
55
60
20
20
DF
Speed Options
30
.
63
65
65
65
25
25
IH
).
IL
16
16
10
5
0
, CE2#= V
68
65
65
70
30
30
IH
88
85
85
85
) or (CE1#=
ACC
Unit
Unit
ns
, t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
33
CE
,