AM29PDL640AGA85NS SPANSION [SPANSION], AM29PDL640AGA85NS Datasheet - Page 36

• Manufacturer Part Number: AM29PDL640AGA85NS
• Description: 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) Pseudo Static RAM
• Manufacturer: SPANSION [SPANSION]

Legend:
DYB = Dynamic Protection Bit
OW = Address (A6:A0) is (0011010)
PD[3:0] = Password Data (1 of 4 portions)
PPB = Persistent Protection Bit
PWA = Password Address. A1:A0 selects portion of password.
PWD = Password Data being verified.
PL = Password Protection Mode Lock Address (A5:A0) is (001010)
RD(0) = Read Data DQ0 for protection indicator bit.
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells in table denote read cycles. All other cycles are
4. During unlock and command cycles, when lower address bits are
5. The reset command returns device to reading array.
6. Cycle 4 programs the addressed locking bit. Cycles 5 and 6
7. Data is latched on the rising edge of WE#.
8. Entire command sequence must be entered for each portion of
9. Command sequence returns FFh if PPMLB is set.
10. The password is written over four consecutive cycles, at
34
Command (Notes)
Reset
SecSi Sector Entry
SecSi Sector Exit
SecSi Protection Bit Program (5, 6)
SecSi Protection Bit Status
Password Program (5, 7, 8)
Password Verify (8, 9)
Password Unlock (7, 10, 11, 17)
PPB Program (5, 6, 12)
All PPB Erase (5, 13, 14)
PPB Lock Bit Set
PPB Lock Bit Status (15, 18)
DYB Write (7)
DYB Erase (7)
DYB Status
PPMLB Program (5, 6, 12)
PPMLB Status (5)
SPMLB Program (5, 6, 12)
SPMLB Status (5)
write operations.
555 or 2AAh as shown in table, address bits higher than A11
(except where BA is required) and data bits higher than DQ7 are
don’t cares.
validate bit has been fully programmed when DQ0 = 1. If DQ0 = 0
in cycle 6, program command must be issued and verified again.
password.
addresses 0-3.
Table 14. Sector Protection Command Definitions
1
3
4
6
4
4
4
4
6
6
3
4
4
4
4
6
4
6
4
Addr Data Addr Data Addr Data
XXX
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
F0
P R E L I M I N A R Y
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
Am49PDL640AG
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
RD(1) = Read Data DQ1 for PPB Lock status.
SA = Sector Address where security command applies. Address bits
A21:A12 uniquely select any sector.
SL = Persistent Protection Mode Lock Address (A5:A0) is (010010)
WP = PPB Address (A6:A0) is (0111010) (Note 16)
EP = PPB Erase Address (A6:A0) is (1111010) (Note 16)
X = Don’t care
PPMLB = Password Protection Mode Locking Bit
SPMLB = Persistent Protection Mode Locking Bit
11. A 2 µs timeout is required between any two portions of password.
12. A 100 µs timeout is required between cycles 4 and 5.
13. A 1.2 ms timeout is required between cycles 4 and 5.
14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been
15. DQ1 = 1 if PPB locked, 0 if unlocked.
16. For all other parts that use the Persistent Protection Bit (excluding
17. Immediately following successful unlock, write the SecSi Sector
18. Immediately following the PPB Lock Status command write the
fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase command
must be issued and verified again. Before issuing erase
command, all PPBs should be programmed to prevent PPB
overerasure.
PDL128G), the WP and EP addresses are 00000010.
Exit command before attempting to verify, program, or erase the
PPBs.
SecSi Sector Exit command before attempting to verify, program,
or erase the PPBs.
C8
88
90
60
60
38
28
60
60
78
58
48
48
58
60
60
60
60
Bus Cycles (Notes 1-4)
PWA[0-3] PWD[0-3]
PWA[0-3] PWD[0-3]
(SA)WP
XX[0-3]
Addr
OW
OW
XX
EP
SA
SA
SA
SA
PL
PL
SL
SL
PD[0-3]
RD(0)
RD(1)
RD(0)
RD(0)
RD(0)
Data
X1
X0
00
68
68
60
68
68
(SA)WP
(SA)EP
Addr
OW
PL
SL
November 20, 2003
Data
48
48
40
48
48
(SA)WP RD(0)
(SA)WP RD(0)
Addr
OW
PL
SL
RD(0)
RD(0)
RD(0)
Data