HDSP-420X Agilent(Hewlett-Packard), HDSP-420X Datasheet - Page 19

• Manufacturer Part Number: HDSP-420X
• Description: 20 mm (0.8 inch) Seven Segment Displays
• Manufacturer: Agilent(Hewlett-Packard)

HDMP-1514 (Rx), Signal Definitions (cont’d.)
674
VCC_TTLA
RX[00:19]
-TCLKSEL
VCC_LOG
VCC_HS1
VCC_HS2
RBC[0:1]
VCC_TTL
Symbol
SPDSEL
VCC_A
PPSEL
PS_CT
NC
Ping-Pong Select
Pin [76]
Power Supply Timing
Cap
Pin [22]
Receive Byte Clocks
Pin [67, 69]
Data Outputs
Pins [43, 62]
Serial Speed Select
Pin [71]
Test Clock Select
Pin [5]
Analog Supply
Pins [77, 78]
High Speed Supply
Pins [13,23,24]
High Speed Supply 2
Pins [15,18]
Logic Power Supply
Pins [33,37,68,72]
TTL Power Supply
Pins [41,42,63,64]
TTL Power Supply
Pin [10]
Pins [11,12,30]
Signal Name
Output
Output
Input
Input
Input
I/O
C
S
S
S
S
S
S
Logic Type
TTL
TTL
TTL
TTL
TTL
A high input instructs the receiver to clock the data
out in ping-pong mode. Byte 0 will be clocked out on
the falling edge of RBC0 and byte 1 will be clocked out
on the falling edge of RBC1. A low input instructs the
receiver to clock both data bytes out on the falling edge
of RBC0.
Pin for connecting the timing capacitor for the power
supervisor circuit.
Two clocks, 180 out of phase, generated from the
recovered data. Used to clock out the two 10 bit data
bytes.
Two, 10 bit, bytes. Byte 0 is comprised of bits
RX[00:09] and byte 1 is comprised of bits RX[10:19].
The serialized bit stream is received TX[00] through
TX[09] then TX[10] through TX[19].
Sets the chip to operate at the serial data rate of 1062.5
Mbaud (high) or 531.25 Mbaud (low).
An applied low selects CLKIN as the serial/bit-rate clock
and bypasses the internal PLL. Used for testing only.
Provides a clean power source for the critical PLL
and high speed analog cells. Normally +5.0 volts.
Provides a clean power source for the high speed
receiver cell I-H50. Noise on this line should be
minimized for best performance. Normally +5.0 volts.
Provides a clean power source for the high speed
receiver cell I-H50. Noise on this line should be
minimized for best performance. Normally +5.0 volts.
Used for all internal PECL logic. Isolate from the
noisy TTL supply. Normally +5.0 volts.
Power supply for all TTL buffer I/O cells. Normally
+5.0 volts.
Power supply for all TTL I/O buffer cells. Normally
+5.0 volts.
No connection.
Description