AM29PDLI27H SPANSION [SPANSION], AM29PDLI27H Datasheet - Page 13

• Manufacturer Part Number: AM29PDLI27H
• Description: 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control
• Manufacturer: SPANSION [SPANSION]

DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
Legend: L = Logic Low = V
A
Notes:
1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the
2. WP#/ACC must be high when writing to sectors 0, 1, 268, or 269.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the OE# and appropriate CE# pins to V
the power control. OE# is the output control and gates
array data to the output pins. WE# should remain at
V
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. Each bank remains
enabled for read access until the command register
contents are altered.
Refer to the
cations and to Figure 11 for the timing diagram. I
the DC Characteristics table represents the active cur-
rent specification for reading array data.
June 30, 2003
Read
Write
Standby
Output Disable
Reset
Temporary Sector Unprotect (High
Voltage)
IN
IH
.
Voltage Sector Protection
= Address In, D
Operation
AC Characteristics
IN
= Data In, D
IL
, H = Logic High = V
section.
OUT
Table 1. Am29PDL127H Device Bus Operations
table for timing specifi-
A D V A N C E
= Data Out
0.3 V
CE#
V
X
X
L
L
IO
L
±
IH
IL
OE#
, V
. CE# is
H
X
H
X
X
L
ID
CC1
Am29PDL127H
= 11.5–12.5 V, V
in
I N F O R M A T I O N
WE#
H
H
X
X
X
L
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device.
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Random Read (Non-Page Read)
Address access time (t
stable addresses to valid output data. The chip enable
access time (t
dresses and stable CE# to valid data at the output in-
puts. The output enable access time is the delay from
the falling edge of the OE# to valid data at the output
inputs (assuming the addresses have been stable for
at least t
Page Mode Read
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read oper-
ation. This mode provides faster read access speed
for random locations within a page. Address bits
A22–A3 select an 8 word page, and address bits
A2–A0 select a specific word within that page. This is
an asynchronous operation with the microprocessor
supplying the specific word location.
The random or initial page access is t
subsequent page read accesses (as long as the loca-
tions specified by the microprocessor falls within that
page) is equivalent to t
(CE#=V
RESET#
V
0.3 V
HH
V
IO
H
H
H
L
ID
±
= 8.5–9.5 V, X = Don’t Care, SA = Sector Address,
Table 1
IH
ACC
), the reassertion of CE# for subsequent ac-
–t
OE
WP#/ACC
X (Note 2)
CE
lists the device bus operations, the in-
time).
) is the delay from the stable ad-
X
X
X
X
X
PACC
ACC
) is equal to the delay from
. When CE# is deasserted
Addresses
(A22–A0)
A
A
A
X
X
X
IN
IN
IN
ACC
or t
DQ15–
High-Z
High-Z
High-Z
High
D
DQ0
D
D
CE
OUT
IN
IN
and
11