AM29PL160C AMD [Advanced Micro Devices], AM29PL160C Datasheet - Page 17

• Manufacturer Part Number: AM29PL160C
• Description: 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only High Performance Page Mode Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

HARDWARE DATA PROTECTION
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 10 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during V
and power-down transitions, or from system noise.
Low V
When V
cept any write cycles. This protects data during V
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets. Subsequent writes are ignored
until V
May 9, 2006 22143C7
(Word Mode)
Addresses
4Ah
4Bh
4Ch
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
CC
CC
CC
is greater than V
Write Inhibit
is less than V
(Byte Mode)
Addresses
8Ch
80h
82h
84h
86h
88h
8Ah
8Eh
90h
92h
94h
96h
98h
LKO
LKO
, the device does not ac-
Table 9. Primary Vendor-Specific Extended Query
. The system must pro-
0050h
0052h
0049h
0031h
0030h
0000h
0002h
0001h
0001h
0004h
0000h
0000h
0002h
Data
CC
D A T A
power-up
Query-unique ASCII string “PRI”
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock
0 = Required, 1 = Not Required
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29LV800A mode
Simultaneous Operation
00 = Not Supported, 01 = Supported
Burst Mode Type
00 = Not Supported, 01 = 4 Word Linear Burst, 02 = 8 Word Linear Burst,
03 = 32 Linear Burst, 04 = 4 Word Interleave Burst
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
Am29PL160C
CC
S H E E T
vide the proper signals to the control pins to prevent
unintentional writes when V
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
the device does not accept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to reading array data on power-up.
IL
, CE# = V
IH
or WE# = V
Description
IL
and OE# = V
IH
CC
. To initiate a write cycle,
is greater than V
IH
during power up,
LKO
.
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