CXA3197 Sony Corporation, CXA3197 Datasheet - Page 19

• Manufacturer Part Number: CXA3197
• Description: 10-bit 125MSPS D/A Converter
• Manufacturer: Sony Corporation

2. MUX.1B mode
Set C1 and C2 Low and C3 High for this mode.
In MUX.1B mode, the frequency of the clock input from the clock input pin is halved internally, and the data is
loaded by this 1/2 frequency-divided signal. The 1/2 frequency-divided signal cannot be observed at this time,
so the data is actually loaded by observing the clock and reset signals to estimate the rising edge of the
internally 1/2 frequency-divided signal. The data can be divided and input to two systems: A (DA0 to DA9) and
B (DB0 to DB9). The data is internally multiplexed, then the system A data is output as an analog signal with a
2-clock pipeline delay, and the system B data as an analog signal with a 3-clock pipeline delay after loading by
the clock.
Internally 1/2 frequency-divided signal
(This signal cannot be observed.)
Reset signal
(when active Low)
Data input signal
Clock
th-rst
ts
After the reset is released, the internal 1/2 frequency-divided signal commences at the first clock edge,
so be sure to input the data in a manner that satisfies the setup time (ts) and hold time (th) with respect
to this clock edge.
ts-rst
th
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Clock input pin
Reset input pin
DA0 to DA9
DB0 to DB9
1/2
CXA3197R (MUX.1B mode)
CXA3197R