CXA3197 Sony Corporation, CXA3197 Datasheet - Page 23

• Manufacturer Part Number: CXA3197
• Description: 10-bit 125MSPS D/A Converter
• Manufacturer: Sony Corporation

In MUX.1A mode, Data A and Data B are internally multiplexed and then the resulting signal can be analog
output. The frequency of the clock is halved by the built-in clock frequency divider circuit and the CLK/2 can be
output at TTL level (DIV2OUT). CLK/2 can be reset by the reset signal.
Block Diagram & Timing Chart (MUX.1A Mode)
(Timing judgment points)
Input Data A
Input Data B
DIV2OUT
PECL
TTL
RESET
DIV2IN
CLK
Input Data A
Input Data B
DIV2OUT
RESET
DIV2IN
CLK
ts-rst
2.0V
(Active High)
(Active Low)
Input Latch A
Input Latch B
0.8V
N$
N$
th-rst
Tpw1 Tpw0
td-DIV
R
D
Q
Q
Latch
Latch
2T-tm
N$
N$
2.0V
0.8V
(Internal)
– 23 –
tm
CLK/2
MUX
0
N +1
ts
N
N$
1
CLK
Analog output
th
N$
t
PD
Latch
2
(A)
N + 2
N + 3
t
PD
N$
(B)
3
tdo
DAC
N$
tdo
t
SET
4
N + 4
N + 5
N
5
Analog out
±1/2LSB
±1/2LSB
CXA3197R
tdo
N + 1