CXA3197 Sony Corporation, CXA3197 Datasheet - Page 21

• Manufacturer Part Number: CXA3197
• Description: 10-bit 125MSPS D/A Converter
• Manufacturer: Sony Corporation

3. MUX.2 mode
Set C1 and C3 Low and C2 High for this mode.
In MUX.2 mode, the clock is input to the clock input pin, and the signal with a cycle half that of the clock
(hereafter, DIV2IN signal) is input to the DIV2IN pin at TTL level. The DIV2IN signal is internally latched by the
clock, so consideration must be given to the setup time (ts_DIV) and hold time (th_DIV) with respect to the
clock. In addition, the data is loaded by the DIV2IN signal, so consideration must also be given to the setup
time (ts) and hold time (th) with respect to the DIV2IN signal. The data can be divided and input to two
systems: A (DA0 to DA9) and B (DB0 to DB9). The data is internally multiplexed, then the system A data is
output as an analog signal with a 2-clock pipeline delay, and the system B data as an analog signal with a 3-
clock pipeline delay from the clock that loads the DIV2IN signal. See the timing chart for the detailed timing.
Analog output signal
System A data
System B data
DIV2IN signal
Clock
A0
B0
ts_DIV
ts
A1
B1
th
0
A0
th_DIV
t
PD
t
(A)
1
PD
A2
B2
B0
(B)
– 21 –
2
A1
3
B1
Clock input pin
DIV2IN input pin
DA0 to DA9
DB0 to DB9
CXA3197R (MUX.2 mode)
CXA3197R