AK4121A AKM [Asahi Kasei Microsystems], AK4121A Datasheet - Page 6

• Manufacturer Part Number: AK4121A
• Description: Asynchronous Sample Rate Converter
• Manufacturer: AKM [Asahi Kasei Microsystems]

(Ta=−40∼85°C; VDD=3.0~3.6V; TVDD=3.0~5.5V; C
Note 8. Min is 8kHz when BYPASS=“H”.
Note 9. BICK rising edge must not occur at the same time as LRCK edge.
Note 10. The AK4121A must be reset by bringing PDN pin “H” to “L” upon power-up.
MS0337-E-02
Parameter
Master Clock Input (MCLK)
L/R clock for Input data (ILRCK)
L/R clock for Output data (OLRCK)
Audio Interface Timing
Power-down & Reset Timing
PDN Pulse Width
Frequency
Duty Cycle
Frequency
Duty Cycle
Input
IBICK Period
IBICK Pulse Width Low
IBICK Pulse Width High
ILRCK Edge to IBICK “↑”
BICK “↑” to ILRCK Edge
SDTI Hold Time from IBICK “↑”
SDTI Setup Time to IBICK “↑”
Output (Slave Mode)
OBICK Period
OBICK Pulse Width Low
OBICK Pulse Width High
OLRCK Edge to OBICK “↑”
OBICK “↑” to OLRCK Edge
OLRCK to SDTO (MSB)
OBICK “↓” to SDTO
Output (Master Mode)
BICK Frequency
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO
Frequency
Duty Cycle
ILRCK period (8KHz ~ 32KHz)
ILRCK period (32KHz ~ 48KHz)
ILRCK period (48KHz ~ 96KHz)
(Note 8)
Slave Mode
Master Mode
SWITCHING CHARACTERISTICS
(Note 9)
(Note 10)
(Note 9)
(Note 9)
(Note 9)
L
=20pF)
- 6 -
Symbol
tMBLR
tBCKH
tBCKH
tBCKL
tBCKL
dBCK
dCLK
fCLK
tBCK
tBCK
fBCK
tBLR
tBLR
tBLR
tLRB
tSDH
tBLR
tLRB
tBSD
tBSD
tSDS
tLRS
Duty
Duty
Duty
tPD
fs
fs
1/256fs+45
1/256fs+25
1/256fs+15
1/64fs
1/64fs
8.192
min
−20
−20
150
40
48
32
48
65
65
30
30
30
65
65
30
30
8
64fs
typ
50
50
50
50
-
-
36.864
max
60
96
52
96
52
30
30
20
30
2007/07
Units
MHz
kHz
kHz
Hz
%
%
%
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
ns
ns
ns