AK4121A AKM [Asahi Kasei Microsystems], AK4121A Datasheet - Page 9

• Manufacturer Part Number: AK4121A
• Description: Asynchronous Sample Rate Converter
• Manufacturer: AKM [Asahi Kasei Microsystems]

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The input port works in slave mode only. The output port works in slave and master mode. An internal system clock is
created by the internal PLL using ILRCK. The MCLK is not needed when the output port is in slave mode, and the
MCLK pin should be connected to DVSS. The CMODE2-0 pins must be controlled when PDN pin =“L”.
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The IDIF2-0 pins select the data mode for the input port. The ODIF1-0 pins select the data mode for the output port. In
all modes the audio data is MSB-first, 2’s compliment format. The SDTO is clocked out on the falling edge of OBICK.
Select these modes when PDN pin=“L”. In BYPASS mode, both IBICK and OBICK are fixed to 64fs.
MS0337-E-02
System Clock
Audio Interface Format
Mode
0
1
2
3
4
5
6
7
Mode
0
1
2
3
Mode
CMODE2
0
1
2
3
4
ODIF1
H
H
H
H
L
L
L
L
H
H
L
L
IDIF2
H
L
L
L
L
CMODE1
ODIF0
H
H
L
L
H
H
H
H
L
L
L
L
IDIF1
H
H
L
L
L
CMODE0
Table 3. Output Audio Data Formats
Table 2. Input Audio Data Formats
20/16bit I
20/16bit MSB Justified
IDIF0
OPERATION OVERVIEW
Table 1. Master/Slave control
16bit LSB Justified
20bit LSB Justified
H
H
H
H
L
L
L
L
H
H
L
L
L
SDTO Format
2
S Compatible
Not used. Set to DVSS
Not used. Set to DVSS
256fso (fso~96kHz)
384fso (fso~96kHz)
512fso (fso~48kHz)
768fso (fso~48kHz)
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20/16bit I
20bit MSB Justified
16bit LSB Justified
20bit LSB Justified
24bit LSB Justified
MCLK
SDTI Format
-
-
2
S Compatible
OBICK (Slave)
≥40fs or 32fs
≥40fs or 32fs
64fs
64fs
Master/Slave (Output Port)
Master (BYPASS mode)
IBICK (Slave)
≥40fs or 32fs
(Reserved)
(Reserved)
Master
Master
Master
Master
OBICK (Master)
Slave
≥32fs
≥40fs
≥40fs
≥48fs
64fs
64fs
64fs
64fs
2007/07