MT9172AE ZARLINK [Zarlink Semiconductor Inc], MT9172AE Datasheet - Page 3

• Manufacturer Part Number: MT9172AE
• Description: ISO2-CMOS ST-BUS FAMILY
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Advance Information
Pin Description (continued)
22
13
14
15
16
17
18
19
20
21
22
Pin #
24
14
15
16
17
19
20
18
21
22
23
24
8,
1,6,
11,
18,
20,
28
16
17
19
21
22
23
25
24
26
27
28
F0o/RCK Frame Pulse Out/Receive Bit Rate Clock output (Digital). In DN mode a 244 ns
L
C4/TCK
DSTi/Di
Precan
OUT
OSC2
OSC1
Name
TEST
V
NC
L
DD
IN
DIS L
Data ST-BUS In/Data In (Digital). A 2.048 Mbit/s serial PCM/data input in DN
mode. In MOD mode this is a continuous bit stream at the bit rate selected.
wide negative pulse indicating the end of the active channel times of the device to
allow daisy chaining. In MOD mode provides the receive bit rate clock to the
system.
Data Clock/Transmit Baud Rate Clock (Digital). A 4.096 MHz TTL compatible
clock input for the MASTER and output for the SLAVE in DN mode. For MOD
mode this pin provides the transmit bit rate clock to the system.
Oscillator Output . CMOS Output.
Oscillator Input . CMOS Input. D.C. couple signals to this pin. Refer to D.C.
Electrical Characteristics for OSC1 input requirements.
Precanceller Disable. When held to Logic ’1
precanceller is forced to V
logic ’0’, the L
internal pulldown (50 k ) is provided on this pin.
No Connection. Leave open circuit
logic “0”, L
pin.
Test Pin.
Receive Signal input (Analog).
Positive Power Supply (+5V) input.
OUT
Disable. When held to logic “1”, L
OUT
Connect to V
OUT
functions normally. An internal pulldown (50 k ) is provided on this
to the precanceller path is enabled and functions normally. An
SS
Bias
.
thus bypassing the precanceller section. When
Description
OUT
is disabled (i.e., output = V
’,
the internal path from L
MT9171/72
Bias
OUT
). When
to the
9-117