ZL30105QDG ZARLINK [Zarlink Semiconductor Inc], ZL30105QDG Datasheet - Page 45

• Manufacturer Part Number: ZL30105QDG
• Description: T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for AdvancedTCA and H.110
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Performance Characteristics* - Functional (continued)
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
10
12
13
14
15
16
17
18
19
20
21
22
11
Output Phase Continuity (MTIE)
E1 (1.8 Hz filter - all reference
frequencies)
PDH Stratum 3 (1.8 Hz filter - all
reference frequencies)
SDH (3.6 Hz filter - all reference
frequencies)
SEC_MSTR = 1 (14 Hz filter - 2 kHz
reference)
SEC_MSTR = 1 (58 Hz filter - 8 kHz
reference)
SEC_MSTR = 1 (922 Hz filter -
1.544 MHz and greater reference
frequencies)
fast lock
Reference switching
Switching from Normal mode to
Holdover mode
Switching from Holdover mode to
Normal mode
DS1 / E1 / PDH Stratum 3
SDH
SEC_MSTR=1: clock redundancy
support
Output Phase Slope
Characteristics
Zarlink Semiconductor Inc.
ZL30105
Min.
40
48
40
25
15
1
1
45
Max.
7.5
9.5
50
50
40
25
15
13
13
61
1
1
0
Units
ms/s
µs/s
µs/s
ns
ns
ns
s
s
s
s
s
s
s
±100 ppm frequency offset,
SEC_MSTR = 0, HMS = 1,
TIE_CLR = 1, and FASTLOCK=0
±9.2 ppm frequency offset,
SEC_MSTR = 0, HMS = 1,
TIE_CLR = 1, and FASTLOCK=0
±9.2 ppm frequency offset,
SEC_MSTR = 0, HMS = 1,
TIE_CLR = 1, and FASTLOCK=0
Up to ±100 ppm frequency offset,
HMS = 1, TIE_CLR = 1, and
FASTLOCK=0
Up to ±100 ppm frequency offset,
HMS = 1, TIE_CLR = 1, and
FASTLOCK=0
Up to ±100 ppm frequency offset,
HMS = 1, TIE_CLR = 1, and
FASTLOCK=0
Up to ±100 ppm frequency offset,
HMS = 1, TIE_CLR = 1, and
FASTLOCK=1
TIE_CLR=1
TIE_CLR=1 and HMS=1
SEC_MSTR=0
SEC_MSTR=0
Notes
Data Sheet