ZL30106_05 ZARLINK [Zarlink Semiconductor Inc], ZL30106_05 Datasheet
ZL30106_05
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ZL30106_05 Summary of contents
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Features • Synchronizes to clock-and-sync-pair to maintain minimal phase skew between inputs and outputs • Supports output wander and jitter generation specifications for SONET/SDH and PDH interfaces • Accepts three input references and synchronizes to any combination of 2 kHz, ...
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Description The ZL30106 SONET/SDH/PDH network interface Digital Phase-Locked Loop (DPLL) provides timing and synchronization for SONET/SDH and PDH network interface cards. The ZL30106 generates SONET/SDH, PDH, ST-BUS and other TDM clock and framing signals that are phase locked to one ...
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Change Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Change Summary Changes from July 2005 Issue to November 2005 Issue. Page, section, figure and table numbers refer to this current issue. Page Item 1 Features 31 Section 6.1 Changes from October 2004 Issue to July 2005 Issue. Page, ...
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Physical Description 2.1 Pin Connections F4/F65o F16o 50 AGND IC 52 REF_SEL0 REF_SEL1 54 REF0 REF_SYNC0 56 REF1 REF_SYNC1 58 REF2 APP_SEL0 TIE_CLR BW_SEL 64 Figure 2 - Pin Connections (64 pin TQFP, please ...
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Pin Description Pin # Name 1 GND Ground Positive Supply Voltage. +1.8 V CORE 3 LOCK Lock Indicator (Output). This output goes to a logic high when the PLL is frequency locked to the selected ...
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Pin # Name 19 RST Reset (Input). A logic low at this input resets the device. On power up, the RST pin must be held low for a minimum of 300 ns after the power supply pins have reached the ...
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Pin # Name 42 C4/C65o Clock 4.096 MHz or 65.536 MHz (Output). This output is used for ST-BUS operation at 2.048 Mbit/s, 4.096 Mbit/s or 65.536 MHz (ST-BUS 65.536 Mbit/s). The output frequency is selected via the OUT_SEL2 pin, see ...
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Pin # Name 55 REF0 Reference (Input). This is one of three (REF0, REF1 and REF2) input reference sources used for synchronization. One of seven possible frequencies may be used: 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, ...
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Reference Monitor The input references are monitored by three independent reference monitor blocks, one for each reference. The block diagram of a single reference monitor is shown in Figure 3. For each reference clock, the frequency is detected and ...
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SCM or CFM failure REF0 dis/requalify timer on REF0 50 ms REF_OOR0 (internal signal) REF_FAIL0 HOLDOVER REF_SEL REF0 REF1 Figure 4 - Behaviour of the Dis/Re-qualify Timer When the incoming signal returns to normal (REF_FAIL=0), the DPLL returns to Normal ...
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C20i Clock Accuracy 0 ppm +4.6 ppm -4.6 ppm -16.6 -13.8 -15 C20: 20 MHz master oscillator clock Figure 6 - Out-of-Range Thresholds for APP_SEL1:0=01 C20i Clock Accuracy 0 ppm +20 ppm -20 ppm -72 -75 -100 C20: 20 MHz ...
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REF_SYNC REF REF frequency REF_SYNC frequency 3.3 Time Interval Error (TIE) Corrector Circuit The TIE Circuit eliminates phase transients on the output clock that may occur during reference switching or the recovery from Holdover mode to Normal mode. On recovery ...
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TIE_CLR = 0 locked to REF0 REF0 REF1 Output Clock locked to REF1 REF0 REF1 Output Clock Figure 9 - Timing Diagram of Hitless Reference Switching The Hitless Mode Switching (HMS) pin enables phase hitless returns from Freerun and Holdover ...
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HMS = 0 Normal mode REF Output Clock Phase drift in Holdover mode REF Output Clock Return to Normal mode REF Output Clock TIE_CLR=0 REF Output Clock Figure 10 - Timing Diagram of Hitless Mode Switching Examples: HMS=1: When ten ...
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Holdover mode - the maximum phase discontinuity in the transition from the Normal mode to the Holdover mode - the maximum phase discontinuity in the ...
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Digitally Controlled Oscillator (DCO) - the DCO receives the limited and filtered signal from the Loop Filter, and based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is dependent on the state of ...
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Control and Modes of Operation 4.1 Application Selection Table 1 lists the applications that are supported by the ZL30106 with the corresponding frequency out of range limits. APP_SEL Application 00 DS1/E1 01 Derived DS1 10 DS2/E2/DS3/E3 11 SONET/SDH Table ...
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Output Clock and Frame Pulse Selection The output of the DCO is used by the frequency synthesizers to generate the output clocks and frame pulses which are synchronized to one of three reference inputs (REF0, REF1 or REF2). These ...
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Holdover Mode Holdover Mode is typically used for short durations while system synchronization is temporarily disrupted. In Holdover Mode, the ZL30106 provides timing and synchronization signals, which are not locked to an external reference signal, but are based on ...
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REF_DIS=0 and REF_CH=0 and HMS=0 RST (HOLDOVER=1) REF_DIS=1: Current selected reference disrupted (see Figure 3) REF_CH= 1: Reference change, a transition in the reference selection (see Figure 14 change in the REF_SEL pins. 4.4.4 Automatic Mode The Automatic ...
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REF_SEL LOCK Note: LOCK pin behaviour depends on phase and frequency offset of REF1. Figure 13 - Reference Switching in Normal Mode 4.5.2 Automatic Reference Switching In the automatic mode of operation (MODE_SEL1:0 = 11), the ZL30106 automatically selects a ...
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In the automatic mode of operation, both pins REF_SEL1 and REF_SEL0 are configured as outputs. The logic level on the REF_SEL0 output indicates the current input reference being selected for synchronization (see Table 6). REF_SEL1 (output pin Table ...
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SCM or CFM failure REF0 REF_DIS0 (internal signal REF_OOR0 (internal signal) REF_FAIL0 HOLDOVER REF_SEL REF0 LOCK Note: This scenario is based on REF1 remaining good throughout the duration. LOCK pin behaviour depends on phase and frequency offset of ...
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Frequency Precision failure REF0 REF_OOR0 (internal signal) REF_FAIL0 HOLDOVER REF_SEL REF0 LOCK Note: This scenario is based on REF1 remaining good throughout the duration. LOCK pin behaviour depends on phase and frequency offset of REF1. Figure ...
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If a clock and frame pulse pair is used for synchronization, the TIE correction value should be cleared by keeping the TIE_CLR pin low for at least 15 ns. Otherwise a static phase offset may remain between the output frame ...
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Measures of Performance The following are some PLL performance indicators and their corresponding definitions. 5.1 Jitter Timing jitter is defined as the high frequency variation of the clock edges from their ideal positions in time. Wander is defined as ...
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Range Pull-in Also referred to as capture range. This is the input frequency range over which the PLL must be able to pull into synchronization. 5.8 Lock Range This is the input frequency range over which the synchronizer must ...
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Applications This section contains ZL30106 application specific details for power supply decoupling, reset operation, clock and crystal operation. 6.1 Power Supply Decoupling Jitter levels on the ZL30106 output clocks may increase if the device is exposed to excessive noise ...
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Consequently, capacitor tolerances and stray capacitances have a major effect on the accuracy of the oscillator frequency. The crystal should be a fundamental mode type - not an overtone. The fundamental mode ...
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Reset Circuit A simple power up reset circuit with about a 60 µs reset low time is shown in Figure 21. Resistor R only and limits current into the RST pin during power down conditions. The reset low time ...
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Characteristics 7.1 AC and DC Electrical Characteristics Absolute Maximum Ratings* Parameter 1 Supply voltage 2 Core supply voltage 3 Voltage on any digital pin 4 Voltage on OSCi and OSCo pin 5 Current on any pin 6 Storage temperature ...
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DC Electrical Characteristics* Characteristics 10 Low-level output voltage * Supply voltage and operating temperature are as per Recommended Operating Conditions. * Voltages are with respect to ground (GND) unless otherwise stated. AC Electrical Characteristics* - Timing Parameter Measurement Voltage Levels ...
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REF0/1/2 output clock with the same frequency as REF F8_32o Figure 23 - REF0/1/2 Input Timing and Input to Output Timing AC Electrical Characteristics* - Input timing for REF_SYNC0/1 (see Figure 24). REF_SYNC0/1 Characteristics frequency 1 REF_SYNC0/1 lead time 2 ...
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AC Electrical Characteristics* - Input to output timing for REF0, REF1 and REF2 references when TIE_CLR = 0 (see Figure 23). Characteristics 1 2 kHz reference input to F2ko delay 2 2 kHz reference input to F8/F32o delay 3 8 ...
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AC Electrical Characteristics output timing (see Figure 25). Characteristics 1 C2o delay 2 C2o pulse width low 3 F4o pulse width low 4 F4o delay 5 C4o pulse width low 6 C4o delay 7 F8o pulse width high ...
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F8o C2o F4o C4o C8o F16o C16o F32o C32o F65o C65o F32o, C32o, F65o and C65o are drawn on a larger scale than the other waveforms in this diagram. Figure Output Timing Referenced to F8/F32o ZL30106 t ...
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AC Electrical Characteristics* - DS1 output timing (see Figure 26). Characteristics 1 C1.5o delay 2 C1.5o pulse width low 3 C3o delay 4 C3o pulse width low 5 Output clock and frame pulse rise time 6 Output clock and frame ...
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AC Electrical Characteristics* - DS2, E2, E3 and DS3 Output Timing (see Figure 28). Characteristics 1 C6o delay 2 C6o pulse width low 3 C8.4o delay 4 C8.4o pulse width low 5 C34o delay 6 C34o pulse width low 7 ...
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AC Electrical Characteristics* - OSCi 20 MHz Master Clock Input Characteristics 1 Oscillator Tolerance - DS1/E1 2 Oscillator Tolerance - Derived DS1 3 Oscillator Tolerance - DS2/DS3/E2/E3 SONET/SDH 4 Duty cycle 5 Rise time 6 Fall time * Supply voltage ...
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Performance Characteristics* - Functional (continued) Characteristics 11 DS2/DS3/E2/E3 (APP_SEL=10) 8 kHz and greater reference frequencies (29 Hz filter) 12 SONET/SDH (APP_SEL=11) 8 kHz and greater reference frequencies (29 Hz filter) 13 BW_SEL=1, all Application modes, all reference frequencies Output Phase ...
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Performance Characteristics*: Output Jitter Generation - ANSI T1.403 conformance Signal measurement DS1 Interface 1 8 kHz to 40 kHz C1.5o (1.544 MHz kHz * Supply voltage and operating temperature are as per Recommended Operating Conditions. ...
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Performance Characteristics*: Measured Output Jitter - Telcordia GR-253-CORE and ANSI T1.105.03 Jitter Generation Requirements Jitter Measurement Signal Filter OC-3 Interface 1 C19o 65 kHz to 1.3 MHz 2 12 kHz to1.3 MHz (Category II) 3 500 Hz to 1.3 MHz ...
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Performance Characteristics* - Unfiltered Jitter Generation Characteristics 1 C1.5o (1.544 MHz) 2 C2o (2.048 MHz) 3 C3o (3.088 MHz) 4 C4o (4.096 MHz) 5 C6o (6.312 MHz) 6 C8o (8.192 MHz) 7 C8.4o (8.448 MHz) 8 C16o (16.384 MHz) 9 ...
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Zarlink Semiconductor 2002 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...