ZL30106_05 ZARLINK [Zarlink Semiconductor Inc], ZL30106_05 Datasheet - Page 16

• Manufacturer Part Number: ZL30106_05
• Description: SONET/SDH/PDH Network Interface DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

The Hitless Mode Switching (HMS) pin enables phase hitless returns from Freerun and Holdover modes to Normal
mode in a single reference operation. A logic low at the HMS input disables the TIE circuit updating the delay value
thereby forcing the output of the PLL to gradually move back to the original point before it went into Holdover mode
(see Figure 10). This prevents accumulation of phase in network elements. A logic high (HMS=1) enables the TIE
circuit to update its delay value thereby preventing a large output phase movement after return to Normal mode.
This causes accumulation of phase in network elements. In both cases the PLL’s output can be aligned with the
input reference by setting TIE_CLR low. Regardless of the HMS pin state, reference switching in the ZL30106 is
always hitless unless TIE_CLR is kept low continuously.
REF1
REF1
REF0
REF0
Output
Clock
Output
Clock
locked to REF1
TIE_CLR = 0
locked to REF0
Figure 9 - Timing Diagram of Hitless Reference Switching
Zarlink Semiconductor Inc.
ZL30106
16
REF0
REF1
REF0
REF1
Output
Clock
Output
Clock
locked to REF1
TIE_CLR = 1
locked to REF0
Data Sheet