ZL30414QGC ZARLINK [Zarlink Semiconductor Inc], ZL30414QGC Datasheet - Page 11
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ZL30414QGC
Manufacturer Part Number
ZL30414QGC
Description
SONET/SDH Clock Multiplier PLL
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL30414QGC.pdf
(24 pages)
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3.2
3.2.1
The C622oP/N-A, C622oP/N-B, C622oP/N-B, and C622oP/N-D outputs provide differential LVPECL clocks at
622.08 MHz. The LVPECL output drivers require a 50 Ω termination connected to the Vcc-2V source for each
output terminal at the terminating end as shown below. The terminating resistors should be placed as close as
possible to the LVPECL receiver.
3.2.2
The C155o output provides a differential CML/LVDS compatible clock at 155.52 MHz. The output drivers require a
50 Ω load at the terminating end if the receiver is CML type.
Recommended Interface circuit
LVPECL to LVPECL Interface
CML to CML Interface
622.08 MHz
155.52 MHz
ZL30414
LVPECL
ZL30414
Driver
GND
GND
Driver
CML
VCC
VCC
C622oN-A
C622oP-A
C155oN
C155oP
Figure 8 - LVPECL to LVPECL Interface
Figure 9 - CML to CML Interface
Typical resistor values: R1 = 130 Ω, R2 =82 Ω
Zarlink Semiconductor Inc.
0.1 uF
0.1 uF
ZL30414
+3.3 V
+3.3 V
Z=50 Ω
Z=50 Ω
11
Z=50 Ω
Z=50 Ω
0.1 uF
0.1 uF
VCC=+3.3 V
50 Ω
Low impedance
DC bias source
R1
R2
50 Ω
R1
R2
LVPECL
Receiver
CML
Receiver
Data Sheet