ZL50015 ZARLINK [Zarlink Semiconductor Inc], ZL50015 Datasheet - Page 20

• Manufacturer Part Number: ZL50015
• Description: Enhanced 1 K Digital Switch with Stratum 4E DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

3.0
The device has sixteen ST-BUS/GCI-Bus inputs (STi0 - 15) and sixteen ST-BUS/GCI-Bus outputs (STio0 - 15).
STio0 - 15 can also be configured as bi-directional pins, in which case STi0 - 15 will be ignored. It is a non-blocking
digital switch with 1024 64 kbps channels and is capable of performing rate conversion between ST-BUS/GCI-Bus
inputs and ST-BUS/GCI-Bus outputs. The ST-BUS/GCI-Bus inputs accept serial input data streams with data rates
of 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and 16.384 Mbps on a per-stream basis. The ST-BUS/GCI-Bus outputs
deliver serial data streams with data rates of 2.048 Mbps, 4.096 Mbps and, 8.192 Mbps and 16.384 Mbps on a
per-stream basis. The device also provides eight high impedance control outputs (STOHZ0 - 7) to support the use
of external ST-BUS/GCI-Bus tristate drivers for the first eight ST-BUS/GCI-Bus outputs (STio0 -7).
By using Zarlink’s message mode capability, microprocessor data stored in the connection memory can be
broadcast to the output streams on a per-channel basis. This feature is useful for transferring control and status
information for external circuits or other ST-BUS/GCI-Bus devices.
The device uses the ST-BUS/GCI-Bus input frame pulse (FPi) and the ST-BUS/GCI-Bus input clock (CKi) to define
the input frame boundary and timing for sampling the ST-BUS/GCI-Bus input streams with various data rates. The
output data streams will be driven by and have their timing defined by FPi and CKi in Divided Slave mode. In
Multiplied Slave mode, the output data streams will be driven by an internally generated clock, which is multiplied
PBGA Pin
H13, H15,
K13, K15,
G12, G13
J14, H12,
K14, J11,
J15, H11,
J12, J13,
Number
M13
P10
G2
Device Overview
LQFP Pin
Number
82, 84,
86, 87,
88, 89,
90, 91,
92, 93,
94, 96,
98, 99
211
41
43
MOT_INTEL
Pin Name
A0 - 13
RESET
IRQ
Zarlink Semiconductor Inc.
Address 0 to 13 (5 V-Tolerant Inputs)
These pins form the 14-bit address bus to the internal memories
and registers.
Motorola_Intel (5 V-Tolerant Input with Enabled Internal
Pull-up)
This pin selects the Motorola or Intel microprocessor interface to
be connected to the device. When this pin is unconnected or
connected to high, Motorola interface is assumed. When this pin is
connected to ground, Intel interface should be used.
Interrupt (5 V-Tolerant Three-state Output)
This programmable active low output indicates that the internal
operating status of the DPLL has changed. An external pull-up
resistor MUST hold this pin at HIGH level.
Device Reset (5 V-Tolerant Input with Internal Pull-up)
This input (active LOW) puts the device in its reset state that
disables the STio0 - 15 drivers and drives the STOHZ0 - 7 outputs
to high. It also preloads registers with default values and clears all
internal counters. To ensure proper reset action, the reset pin must
be low for longer than 1 µs. Upon releasing the reset signal to the
device, the first microprocessor access cannot take place for at
least 600 µs due to the time required to stabilize the device and
the crystal oscillator from the power-down state. Refer to Section
Section 17.2 on page 46 for details.
ZL50015
20
Description
Data Sheet