ZL50015 ZARLINK [Zarlink Semiconductor Inc], ZL50015 Datasheet - Page 90

• Manufacturer Part Number: ZL50015
• Description: Enhanced 1 K Digital Switch with Stratum 4E DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

ZL50015
Data Sheet
25.0
Applications
This section contains application-specific details for clock and crystal operation and power supply decoupling.
25.1
OSCi Master Clock Requirement
The device requires a 20 MHz master clock source at the OSCi pin when operating in Master mode or in Divided
Slave with OSC mode. The clock source may be either an external clock oscillator connected to the OSCi pin, or an
external crystal connected between the OSCi and OSCo pins. If an external clock source is present, OSC_EN must
be tied high.
Note that using a crystal is only suitable for wider tolerance applications (e.g., ±100 ppm). For stratum 4E
applications a clock oscillator with a tolerance of ±32 ppm should be used. See Application Note ZLAN-68 for a list
of Oscillators and Crystals that can be used with Zarlink PLL’s and Digital Switches with embedded PLL’s.
25.1.1
External Crystal Oscillator
When an external crystal oscillator is used, a complete oscillator circuit made up of a crystal, resistor and capacitors
is shown in Figure 23 on page 90. XC is a buffered version of the 20 MHz input clock connected to the internal
circuitry.
1 K DX
OSCi
20 MHz
Ω
1 Μ
25 pF
25 pF
OSCo
XC
Figure 23 - Crystal Oscillator Circuit
The accuracy of a crystal oscillator circuit depends on the crystal tolerance as well as the load capacitance
tolerance. Typically, for a 20 MHz crystal specified with a 32 pF load capacitance, each 1 pF change in load
capacitance contributes approximately 9 ppm to the frequency deviation. Consequently, capacitor tolerances and
stray capacitances have a major effect on the accuracy of the oscillator frequency. The trimmer capacitor shown in
Figure 23 on page 90 may be used to compensate for capacitive effects.
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Zarlink Semiconductor Inc.