AM7968 AMD [Advanced Micro Devices], AM7968 Datasheet - Page 89

• Manufacturer Part Number: AM7968
• Description: TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface)
• Manufacturer: AMD [Advanced Micro Devices]

Figure 7-10
Figure 7-11
CNB
CSTRB
CNB
SERIN +
DSTRB
SERIN+
IGM
IGM
SERIN -
output data at the same time This also guarantees that the CNB on the first Receiver
goes active (HIGH) within 2 gate delays + 20 ns after it goes LOW. This leaves enough
time for the first Receiver to capture the (R+1)th byte of data.
TAXI Receiver—Cascaded In Auto-Repeat Configuration.
Configuration 2
TAXI Receiver—Cascaded in Auto-Repeat Configuration.
Configuration 3
In practice, all the AND gates are not required. Using the above equation for X we can
calculate a value of R1 for which X is less than 1 byte period at the appropriate fre-
quency of operation. Then if the number of receivers to be cascaded is greater than R1,
an AND gate is needed for every (R1+1)th Receiver in cascade. The other receivers can
be directly connected as shown in Figure 7-11.
Syncs in Auto-Repeat Configuration and Recovering from Errors
A Sync in Auto-Repeat Configuration acts much like a Sync in Normal Cascade mode. It
resets all the Receivers and their IGMs so the upstream (Primary) Receiver receives the
next non Sync byte of data. This remains as the method of recovering from byte framing
errors.
7.4 Unbalanced Configuration (Am7968/Am7969-125 Only)
In reality there is no difference in connection between balanced and Unbalanced
Configurations. The name only indicates that the number of Transmit bytes and the
number of Receive bytes are unequal.
The TAXI Receivers do not care how many data bytes the Transmitter is sending to
them. One data byte can be transmitted to several Receivers. The only limitation here is
SERIN–
CNB
CSTRB
TAXIchip Integrated Circuits Technical Manual
CNB
DSTRB
IGM
IGM
CNB
CSTRB
CNB
DSTRB
IGM
IGM
CNB
CSTRB
CNB
DSTRB
IGM
IGM
12330E-33
AMD
12330E-32
85