ZL50023GAC ZARLINK [Zarlink Semiconductor Inc], ZL50023GAC Datasheet - Page 25

• Manufacturer Part Number: ZL50023GAC
• Description: Enhanced 4 K Digital Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

8.4
In addition to the output bit advancement, the device has a fractional output bit advancement feature that offers
better resolution. The fractional output bit advancement is useful in compensating for varying parasitic load on the
serial data output pins.
By default all of the streams have zero fractional bit advancement such that bit 7 is the first bit that appears after the
output frame boundary. The fractional output bit advancement is enabled by STO[n]FA 1 - 0 (bits 8 - 7) in the
Stream Output Control Register 0 - 31 (SOCR0 - 31). For all streams running at any data rate except 16.384 Mbps
the fractional bit advancement can vary from 0, 1/4, 1/2 to 3/4 bits. For streams operating at 16.384 Mbps, the
fractional bit advancement can be set to either 0 or 1/2 bit.
8.5
The external high impedance signals can be programmed to better match the timing required by the external
buffers. By default, the output timing of the STOHZ signals follows the programmed channel delay and bit offset of
their corresponding ST-BUS/GCI-Bus output streams. In addition, for all high impedance streams operating at any
data rate except 16.384 Mbps, the user can advance the STOHZ signals a further 0, 1/4, 1/2, 3/4 or 4/4 bits by
programming STOHZ[n]A 2 - 0 (bit 11 - 9) in the Stream Output Control Register. When the stream is operating at
16.384 Mbps, the additional STOHZ advancement can be set to 0, 1/2 or 4/4 bits by programming the same
register.
STio[n]
STo[n]FA1-0
(2, 4 or 8Mbps)
STo[n]FA1-0 = 01
(16 Mbps)
STio[n]
STo[n]FA1-0 = 11
(2, 4 or 8 Mbps)
FPi
STio[n]
STo[n]FA1-0 = 00
(Default 2, 4, 8 or
16Mbps)
STio[n]
STo[n]FA1-0 = 01
(2, 4 or 8 Mbps)
Fractional Output Bit Advancement Programming
External High Impedance Control Advancement
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively.
=
Figure 15 - Output Fractional Bit Advancement Timing Diagram (ST-BUS)
10
2
1
Last Channel
1
Last Channel
Last Channel
Last Channel
1
1
0
Zarlink Semiconductor Inc.
0
ZL50023
0
0
25
7
7
Channel 0
7
Fractional Bit Advancement = 1/4 Bit
Fractional Bit Advancement = 1/2 Bit
Channel 0
Fractional Bit Advancement = 3/4 Bit
7
Channel 0
Channel 0
6
6
6
6
5
5
5
5
4
Data Sheet
4
4