ZL50023GAC ZARLINK [Zarlink Semiconductor Inc], ZL50023GAC Datasheet - Page 71

• Manufacturer Part Number: ZL50023GAC
• Description: Enhanced 4 K Digital Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc-
* Test condition is R
AC Electrical Characteristics
1
2
3
4
the time taken to discharge C
tion testing.
STio Delay - Active to High-Z
STio Delay - High-Z to Active
Output Drive Enable (ODE) Delay
- High-Z to Active
Output Drive Enable (ODE) Delay
- Active to High-Z
ODE
STio
CKi @ 4.096MHz
CKi @ 8.192MHz
CKi @ 16.384MHz
CKi @ 4.096MHz
CKi @ 8.192MHz
CKi @ 16.384MHz
Characteristic
L
= 1 k, C
t
ZD_ODE
HiZ
L
L
= 30 pF; high impedance is measured by pulling to the appropriate rail with R
.
†
- ST-BUS/GCI-Bus Output Tristate Timing
CKo0
FPo0
STio
STio
Figure 33 - Serial Output and External Control
Figure 34 - Output Drive Enable (ODE)
Valid Data
t
t
ZD_ODE
DZ_ODE
Sym.
Zarlink Semiconductor Inc.
t
t
DZ
ZD
Valid Data
ZL50023
Tristate
t
DZ_ODE
71
Min.
-3
-8
-3
-8
t
t
DZ
ZD
V
Typ.
CT
Valid Data
Tristate
‡
V
HiZ
CT
Max.
260
138
260
138
77
77
77
77
7
0
7
0
V
V
CT
CT
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
L
, with timing corrected to cancel
Multiplied Clock Mode
Divided Clock Mode
Multiplied Clock Mode
Divided Clock Mode
Multiplied Clock Mode
Divided Clock Mode
Multiplied Clock Mode
Divided Clock Mode
Test Conditions
Data Sheet
V
V
CT
CT
*