ZL50031QEG1 ZARLINK [Zarlink Semiconductor Inc], ZL50031QEG1 Datasheet - Page 45
ZL50031QEG1
Manufacturer Part Number
ZL50031QEG1
Description
Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 2 K x 2 K Local Switch
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50031QEG1.pdf
(74 pages)
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7 - 4
Bit
Read/Write Address: 002B
Reset Value: 0000
CNEN
15
FP1 - 0
SS3 - 0
Name
BEN
14
H
AEN
PRI_REF Frequency Selection Bits: These bits are used to select different clock
frequencies for the primary reference.
Secondary Clock Reference Input Selection Bits: These bits are used to select secondary
reference input.
13
Table 19 - DPLL Operation Mode (DOM1) Register Bits (continued)
H
SS3 - SS0
RPS
12
FS1
0000
0001
0010
0100
0101
1000
1001
1010
0011
0110
0111
1011
1100
1101
1110
1111
0
0
1
1
FS1
11
FS0
10
Secondary Clock Reference Input
FS0
Zarlink Semiconductor Inc.
FP1
0
1
0
1
9
ZL50031
FP0
8
“A Clocks”
“B Clocks”
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CTREF1
CTREF2
LREF0
LREF1
LREF2
LREF3
45
8 kHz
1.544 MHz
2.048 MHz
8.192 MHz (“A Clocks” or “B Clocks”)
SS3
7
Description
SS2
Primary Reference
6
SS1
5
SS0
4
SP3
3
SP2
2
SP1
1
Data Sheet
SP0
0
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