ZL50031QEG1 ZARLINK [Zarlink Semiconductor Inc], ZL50031QEG1 Datasheet - Page 48

• Manufacturer Part Number: ZL50031QEG1
• Description: Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 2 K x 2 K Local Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

4 -3
1- 0
Bit
2
Reserved
CNS1 - 0
DIV1 - 0
Name
Table 20 - DPLL Operation Mode (DOM2) Register Bits (continued)
Divider Bits: These two bits define the relationship between the input reference
and the NREFo output.
Reserved. In normal functional mode, this bit MUST be set to zero.
NREFo Source Selection Bits: These three bits select three of the LREF3 -
LREF0 to be the NREFo source.
DIV1
0
0
1
1
CNS1
0
0
1
1
Zarlink Semiconductor Inc.
DIV0
0
1
0
1
ZL50031
CNS0
Input reference
Input reference/193 (8 kHz signal when input reference
clock = 1.544 MHz)
Input reference/256 (8 kHz signal when input reference
clock = 2.048 MHz)
Reserved
48
0
1
0
1
Description
NREFo Output
NREFo Source
LREF0
LREF1
LREF2
LREF3
Data Sheet