AM79C930VC/W AMD [Advanced Micro Devices], AM79C930VC/W Datasheet - Page 134
![no-image](/images/no-image-200.jpg)
AM79C930VC/W
Manufacturer Part Number
AM79C930VC/W
Description
PCnet-Mobile Single-Chip Wireless LAN Media Access Controller
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM79C930VCW.pdf
(161 pages)
- Current page: 134 of 161
- Download datasheet (678Kb)
PCMCIA I/O WRITE ACCESS
Notes:
1. The max value for this parameter assumes the following worst case situation:
2. Parameter is not included in production test.
134
Value
0
1
2
3
4
5
6
7
Parameter
AMD
Symbol
tWTLWTH
tIWHRGH
tWTHIWH
tRGLIWL
tIWLWTL
tIWLIWH
tIWHAX
tIWHEH
tDVIWL
tIWHDX
tAVIWL
tELIWL
Worst Case
FLASH and SRAM wait states set at “3.”
Host performs PCMCIA WRITE cycle at same time that Am79C930 embedded 80188 controller begins
instruction fetch cycle to FLASH memory.
PCMCIA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188
controller access.
Host performs PCMCIA READ cycle immediately following completion of PCMCIA WRITE cycle.
After completion of first embedded 80188 access to FLASH, posted PCMCIA WRITE executes to SRAM;
PCMCIISA READ stycle is being held in wait state.
After completion of posted PCMCIA WRITE cycle, new embedded 80188 access to FLASH begins.
After completion of second embedded 80188 access to FLASH, PCMCIA READ cycle is allowed to proceed onto
memory bus to SRAM; host is still held in wait state.
At SRAM READ cycle completion, data is delivered to PCMCIA bus and wait state is exited.
Parameter Description
Address setup to IOWR
Address hold from IOWR
REG setup to IOWR
REG hold from IOWR
CE setup to IOWR
CE hold from IOWR
IOWR width
WAIT
WAIT width
IOWR
Data setup to IOWR
Data hold from IOWR
delay from IOWR
from WAIT
P R E L I M I N A R Y
Am79C930
Test Conditions
Notes 1, 2
Min
165
70
20
20
60
30
5
0
5
0
53 X TCLKIN
Max
35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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