AM79C974KCW AMD [Advanced Micro Devices], AM79C974KCW Datasheet - Page 34
AM79C974KCW
Manufacturer Part Number
AM79C974KCW
Description
PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM79C974KCW.pdf
(153 pages)
- Current page: 34 of 153
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Basic Non-Burst Write
All Am79C974 controller non-burst write accesses are
of the PCI command type Memory Write (type 7).
Figure 8 shows two non-burst write access within one
arbitration cycle. The Am79C974 controller will drop
FRAME between two consecutive non-burst write cy-
cles. The Am79C974 controller will re-request the bus
34
DEVSEL
FRAME
AMD
TRDY
IRDY
C/BE
REQ
GNT
PAR
CLK
AD
1
DEVSEL is sampled by the Am79C974 controller.
Figure 8. Non-Burst Write Cycles With and Without Wait States
2
3
ADDR
0111
4
P R E L I M I N A R Y
DATA
BE's
PAR
5
Am79C974
PAR
6
immediately if it is preempted before starting the second
access. The example below shows an extended cycle
for the first access. The target asserts DEVSEL 2 clock
cycles after the address phase (FRAME asserted) and
adds one extra wait state by asserting TRDY only on
clock 7. The second write cycle in the example shows a
ZERO wait state access.
7
8
ADDR
0111
9
DATA
BE's
PAR
10
PAR
11
18681A-12
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