AM79C974KCW AMD [Advanced Micro Devices], AM79C974KCW Datasheet - Page 35
AM79C974KCW
Manufacturer Part Number
AM79C974KCW
Description
PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM79C974KCW.pdf
(153 pages)
- Current page: 35 of 153
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DEVSEL
FRAME
Basic Burst Read Cycles
All Am79C974 controller burst read transfers are of the
PCI command type Memory Read Line (type14).
AD[1:0] will both be ZERO during the address phase in-
dicating a linear burst order. All four byte enable signals
will be ZERO during the data phase as the Am79C974
controller always reads a full 32-bit word when in burst
TRDY
IRDY
C/BE
REQ
GNT
PAR
CLK
AD
1
DEVSEL is sampled by the Am79C974 controller.
2
3
ADDR
1110
4
PAR
Figure 9. Burst Read Cycles
5
0000
P R E L I M I N A R Y
DATA
Am79C974
6
PAR
mode.
Figure 9 shows a typical burst read access. The
Am79C974 controller arbitrates for the bus, is granted
access, and reads four 32-bit words (DWORD) from
system memory and then releases the bus. All four data
phases in this example take two clock cycles each,
which is determined by the timing of TRDY.
7
DATA
8
PAR
9
DATA
10
PAR
11
DATA
12
AMD
18681A-13
PAR
13
35
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