ZL50074GAC ZARLINK [Zarlink Semiconductor Inc], ZL50074GAC Datasheet - Page 26

• Manufacturer Part Number: ZL50074GAC
• Description: 32 K x 32 K Channel TDM Switch with 128 Input and 128 Output Streams
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

9.0
9.1
The PWR pin is used to reset the ZL50074. When this pin is low, the following functions are performed:
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9.2
The ZL50074 has two separate power supplies: V
power-up sequence is for V
V
9.3
Upon power up, the ZL50074 should be initialized as follows:
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DD_IO
Asynchronously puts the microprocessor port in a reset state
Tristates all of the output streams (SToA0 - 31, SToB0 - 31, SToC0 - 31, SToD0 - 31)
Preloads all of the registers with their default values (refer to the individual registers for default values)
Clears all internal counters
Assert PWR to low immediately after power is applied
Set the TRST pin low to disable the JTAG TAP controller
Deassert the PWR pin.
Apply the Master Clock Input (CKi0) and Master Frame Pulse Input (FPi0) to the values defined by the
CK_SEL1 - 0 pins
Set the ODE pin low to disable the output streams
Device Reset and Initialization
Power Supply Sequencing
Initialization
Power-up and Initialization of the ZL50074
supply by more than 0.3 V. Both supplies may be powered-down simultaneously.
Address
SIZ1 - 0
BERR
WAIT
Data
R/W
DTA
CS
DS
The cycle termination signals WAIT & DTA are provided for all bus configurations.
Hi-Z
Hi-Z
DD_IO
to be applied first, followed by the V
Figure 7 - Write Cycle Operation
Zarlink Semiconductor Inc.
ZL50074
DD_IO
26
(3.3 V) and V
DD_CORE
DD_CORE
supply. V
(1.8 V). The recommended
Hi-Z
DD_CORE
should not lead
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