ZL50074GAC ZARLINK [Zarlink Semiconductor Inc], ZL50074GAC Datasheet - Page 38
![no-image](/images/no-image-200.jpg)
ZL50074GAC
Manufacturer Part Number
ZL50074GAC
Description
32 K x 32 K Channel TDM Switch with 128 Input and 128 Output Streams
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50074GAC.pdf
(61 pages)
- Current page: 38 of 61
- Download datasheet (571Kb)
The Group Control Register is a static control register. Changes to bit settings may disrupt data flow on the selected
port for a maximum of 2 frames.
1 - 0
External Read/Write Address: 40200
Reset Value: 000C000C
Bit
31
15
0
0
30
14
0
0
ISSRC1 - 0
Name
29
13
0
0
28
12
0
0
H
27
11
Input Stream Clock Source Select
0
0
Table 21 - Group Control Register (continued)
H
ISSRC1 - 0
26
10
- 4027F
0
0
00
01
10
11
25
ISI
0
9
H
ISPD
24
8
Zarlink Semiconductor Inc.
0
4
ZL50074
ISPD
23
7
Internal System Clock
0
3
Input Timing Source
38
CKi0 and FPi0
CKi1 and FPi1
CKi2 and FPi2
ISPD
OSI
22
6
2
Description
OSBA
ISPD
21
5
1
1
OSBA
ISPD
20
4
0
0
19
1
3
1
18
1
2
1
OSSRC
ISSRC
17
1
1
1
Data Sheet
OSSRC
ISSRC
16
0
0
0
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