AM79Q4457J ETC1 [List of Unclassifed Manufacturers], AM79Q4457J Datasheet - Page 27

• Manufacturer Part Number: AM79Q4457J
• Description: Quad Subscriber Line Audio Processing Circuit-Non-Programmable (QSLAC-NP) Devices
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

Power Down (PDN
0 — Powers the channel up
1 — Powers the channel down
Reset State
All four channel control registers are reset by the appli-
cation of power. This resets the QSLAC-NP device to
the following state: TGS, RGS, BNS = 0 and PDN = 1
for all four channels.
Signal Processing
Overview of Digital Filters
Several elements in the signal processing section of
the Am79Q4457 device provide user options. These
options allow the user to optimize the performance of
the QSLAC-NP device for the application. Figure 8
shows the QSLAC-NP device signal processing sec-
tion and indicates the user-programmable blocks, the
reference current selector, the reference voltage selec-
tor, the balance network selector, and the A-law/µ-law
selector. The High-Pass Filter (HPF) and the Low-
Pass Filter (LPF) sections of the signal processor
are implemented in the digital domain. The advan-
tages of digital filters are high reliability, no drift with
time or temperature, unit-to-unit repeatability, and
superior transmission performance.
Transmit Signal Processing
In the transmit path, the analog input signal (I
converted, filtered, compressed, and made available to
the PCM highway in A-law or µ-law form. The signal
processor contains an ALU, RAM, ROM, and control
logic to implement the filter sections.
The decimator reduces the high input sampling rate to
16 kHz for input to the Low-Pass and High-Pass Filters.
The High-Pass Filter rejects low frequencies such as
50 Hz or 60 Hz and the Low-Pass Filter limits the
voice band to 3400 Hz.
Transmit PCM Interface
The transmit PCM interface receives 1 byte (8 bits)
every 125 µs from the A-law/µ-law compressor. The
data is transmitted onto the PCM highway under con-
trol of the transmit logic, synchronized by the Transmit
Frame Synchronization signal (FSX
chronization signal (FSX
slot of the PCM frame for Channel N. The QSLAC-NP
devices (Am79Q4457/5457) are compatible with both
a long- and a short-frame synchronization signal. See
the PCM interface timing specifications (20 to 24) for
more details. While the PCM data is output on the
DXA port, the TSCA buffer control signal is Low.
n
):
N
) identifies the transmit time
N
). The frame syn-
IN
) is A/D
SLAC Products
Receive Signal Processing
Digital data received from the PCM highway is ex-
panded from A-law or µ-law, filtered, converted to ana-
log, and passed to the V
contains an ALU, RAM, ROM, and control logic to im-
plement the filter sections.
The Low-Pass Filter band limits the signal. The interpo-
lator increases the sampling rate prior to D/A conver-
sion.
Receive PCM Interface
The receive PCM interface receives 1 byte (8 bits)
every 125 µs from the PCM highway. The data is re-
ceived under control of the receive logic and synchro-
nized by the receive frame synchronization signal
(FSR
the receive time slot of the PCM frame for Channel N.
The QSLAC-NP devices (Am79Q4457/5457) are com-
patible with both a long- and a short-frame synchroni-
z a t i o n s i g n a l . S e e t h e P C M i n t e r fa c e t i m in g
specifications (20 to 24) for more details. The receive
PCM data is expanded by the A-law/µ-law expansion
logic, and passed on to the signal processor.
Speech Coding
The A/D and D/A conversions follow either the A-law or
the µ-law standard as defined in ITU-T Recommenda-
tion G.711. A-law or µ-law operation is programmed
using the A-law/µ-law program (A/µ) pin. Alternate bit
inversion is performed as part of the A-law coding.
Short-Frame Sync Mode
If each of the transmit (FSX
lap either one or two negative-going transitions of
PCLK, the part operates in what is called Short-Frame
Sync mode. In this mode, the part operates like a
DSLAC, ASLAC, or QSLAC device programmed for
time slot 0, clock slot 0, and XE=1. If a frame sync over-
laps two transitions, the first of these transitions de-
fines the beginning of the time slot.
The first positive PCLK transition after the beginning of
a transmit time slot enables the DXA output with the
sign bit as the first output. It also drives the TSCA out-
put Low. The succeeding seven positive clock transi-
tions shift out the remainder of the data, and the eighth
negative transition tri-states DXA and turns off TSCA.
During the latter part of each output period, the trans-
mit data is held by a weak driver in order to minimize
bus contention if one time slot starts before the preced-
ing one ends.
The first negative PCLK transition after the beginning
of a receive time slot latches in the first data bit (sign
bit) from the DRA input. The succeeding seven nega-
tive clock transitions shift in the remainder of the data.
N
). The receive frame sync (FSX
OUT
N
pin. The signal processor
) frame sync pulses over-
N
) pulse identifies
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