AM79Q4457J ETC1 [List of Unclassifed Manufacturers], AM79Q4457J Datasheet - Page 9

• Manufacturer Part Number: AM79Q4457J
• Description: Quad Subscriber Line Audio Processing Circuit-Non-Programmable (QSLAC-NP) Devices
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

Power Supply for the Am79Q4457/5457
Devices:
AGND
DGND
V
V
Two separate power supply inputs are provided to allow
for noise isolation and good power supply decoupling
techniques; however, the two pins have a low imped-
ance connection inside the part. For best performance,
all of the +5.0 power supply pins should be connected to-
gether at the connector of the printed circuit board, and
all of the grounds should be connected together at the
connector of the printed circuit board.
PDN
PDN
V
V
V
CCA
CCD
Pin Name
OUT1
OUT3
REF2
MCLK
PCLK
TSCA
V
1
3
, PDN
, V
REF1
, PDN
, V
, V
OUT2
OUT4
REF3
2
4
,
,
Analog Ground
Digital Ground
+5.0 V Analog Power Supply
+5.0 V Digital Power Supply
Voltage
Output
Output
Type
Input
Input
Input
Input
Master Clock. The Master Clock frequency can be 1.536 MHz, 1.544 MHz, 2.048 MHz, or 4.096
MHz for use by the digital signal processor. Using the Transmit Frame Sync (FSX) Inputs, the
QSLAC-NP device determines the MCLK frequency and makes the necessary internal
adjustments automatically. The master clock frequency must be an exact integer multiple of the
frame sync frequency.
PCM Clock. The PCM clock determines the rate at which PCM data is serially shifted into or out
of the PCM ports. PCLK is an integer multiple of the frame sync frequency. The maximum clock
frequency is 4.096 MHz, and the minimum clock frequency is 256 kHz, due to a single PCM
highway. PCLK frequencies between 1.03 MHz and 1.53 MHz are not allowed. The digital signal
processor clock can be derived from PCLK by connecting MCLK and PCLK together. See frequency
restrictions under MCLK.
(Am79Q5457 Device Only) Power Down. The power-down inputs provide direct control over the
channel circuitry. A logic High on PDN
powers the channel up. PDN
Channel 3, and PDN
circuitry. Refer to the Power-Up Sequence section on 24 for initialization using the PDN pins.
Time Slot Control. The Time Slot Control output is an open drain output (requiring a pull-up resistor to
V
on the DXA pin for any of the four channels.
Analog Outputs. The received digital data at DRA is processed and converted to an analog signal
at the V
output from Channel 3; and V
to V
Voltage Reference. The V
larger) to be connected from V
reference. V
2.1 V, and the output resistance is 115 kW. The leakage current in the capacitor must be less
than 20 nA. A larger filter capacitor will provide better filtering, but will increase the settling time.
(Am79Q4457 Device Only). Voltage Reference. V
alternative reference voltages for the channel Digital-to-Analog (D-to-A) converters. The D-to-A
converters decode the received PCM data into analog voltage levels. V
selected by the Receive Gain Select (RGS) bits as the reference for the D-to-A converter in order to
select the receive gain of the channel.
CCD
REF1
) and is normally inactive (high impedance). TSCA is active (Low) when PCM data is transmitted
OUT
.
pin. V
REF1
is buffered before it is used by internal circuitry. The voltage on V
OUT1
4
is the output from Channel 1; V
controls Channel 4. The PDN pins are used in the initialization of the internal
SLAC Products
REF1
1
OUT4
output is provided in order for an external 0.1-µF capacitor (or
controls Channel 1, PDN
REF1
is the output for Channel 4. The V
to ground, filtering noise present on the internal voltage
n
(n = 1 to 4) powers Channel n down while a logic Low
Description
REF2
OUT2
and V
2
is the output for Channel 2; V
controls Channel 2, PDN
REF3
are buffered and are available as
OUT
REF1
voltages are referenced
, V
REF2
, or V
REF1
3
controls
OUT3
is nominally
REF3
can be
is the
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