ZL50404GDC ZARLINK [Zarlink Semiconductor Inc], ZL50404GDC Datasheet - Page 75
![no-image](/images/no-image-200.jpg)
ZL50404GDC
Manufacturer Part Number
ZL50404GDC
Description
Lightly Managed/Unmanaged 5-Port 10/100M Ethernet Switch
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50404GDC.pdf
(121 pages)
- Current page: 75 of 121
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13.3.4.15
CPU Address:h330-336
Accessed by CPU, (R/W)
CPU Queue insertion command
13.3.4.16
CPU Address:h337
Accessed by CPU, (RO)
CPU command queue status
13.3.4.17
CPU Address:h338-339
Accessed by CPU, (RO)
55
CQ6
15
CG1
Bit[3:0]:
Bit[7:4]:
Bit[9:8]:
Bit [13:10]
Bit [20:14]
Bit [35:21]
Bit [50:36]
Bit [51]
Bit [54:52]
Bit [55]
Bit [0]:
Bit [1]:
CPUQINS0 - CPUQINS6 – CPU Queue Insertion Command
CPUQINSRPT – CPU Queue Insertion Report
CPUGRNHDL0 - CPUGRNHDL1 – CPU Allocated Granule Pointer
CQ5
The command is under processing.
Insertion Fail (May be due to queue full, WRED or filtering)
Destination Map (port 3-0).
Reserved. Must be 0.
Destination Map (MMAC, CPU).
Priority
Number of granules for the frame
Tail pointer
Header Pointer
Multicast frame (has to be one if more than one destination port)
Reserved
Command valid (will be processed on the rising edge of the signal)
CG0
CQ4
0
CQ3
Zarlink Semiconductor Inc.
ZL50404
CQ2
75
CQ1
CQ0
0
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