ZL50404GDC ZARLINK [Zarlink Semiconductor Inc], ZL50404GDC Datasheet - Page 93

• Manufacturer Part Number: ZL50404GDC
• Description: Lightly Managed/Unmanaged 5-Port 10/100M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

13.3.7.15
CPU Address:h613, h614
Accessed by CPU (R/W)
The registers define the operation code if MAC control frame is forced out by processor.
13.3.7.16
I²C Address 0BF, CPU Address:h620
Accessed by CPU and I²C (R/W)
13.3.7.17
I²C Address 0C0, CPU Address:h621
Accessed by CPU and I²C (R/W)
13.3.7.18
I²C Address 0C1, CPU Address:h622
Accessed by CPU and I²C (R/W)
13.3.8
13.3.8.1
CPU Address 70C
Accessed by CPU (R/W) (Default 00)
(Group 7 Address) Port Mirroring Group
Bit [7:0]
Bit [7:0]
Bit [7:0]
Bit [3:0]:
Bit [4]
Bit [5]
Bit [6]:
Bit [7]:
MIRROR CONTROL – Port Mirror Control Register
FCB Base Address Register 0
FCB Base Address Register 1
FCB Base Address Register 2
fMACCReg0, fMACCReg1 - MAC Control Frame OpCode
FCB Base address bit 7:0 (Default 0)
FCB Base address bit 23:16 (Default 0)
Destination port to be mirrored to.
Mirror Flow from MIRROR_SRC_MAC[5:0] to MIRROR_DEST_MAC[5:0]
Mirror Flow from MIRROR_DEST_MAC[5:0] to MIRROR_SRC_MAC[5:0]
Mirror when address is destination
Mirror when address is source
FCB Base address bit 15:8 (Default 0x60)
Zarlink Semiconductor Inc.
ZL50404
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Data Sheet