ZL50418GKC ZARLINK [Zarlink Semiconductor Inc], ZL50418GKC Datasheet - Page 104
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ZL50418GKC
Manufacturer Part Number
ZL50418GKC
Description
Managed 16-Port 10/100 M + 2-Port 1 G Ethernet Switch
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50418GKC.pdf
(163 pages)
- Current page: 104 of 163
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14.10.7
CPU Address:h606
Accessed by CPU and serial interface only (R/W)
Note : Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then
program MII command. Writing this register will initiate a serial management cycle to the MII management
interface.
14.10.8
CPU Address:h607
Accessed by CPU and serial interface only (RO)
•
14.10.9
CPU Address:h608
Accessed by CPU and serial interface only (RO)
•
14.10.10
CPU Address:h609
Accessed by CPU, serial interface and I
•
•
•
Bit [7:0] - MII Data [7:0]
Bit [7:0] - MII Data [15:8]
Bits [4:0] -
Bit [6] -
Bit [7] -
•
•
•
•
MIIC3 – MII Command Register 3
MIID0 – MII Data Register 0
MIID1 – MII Data Register 1
LED Mode – LED Control
Bit [0]
Bit [2:1]:
Bit [4:3]:
Bit [7:5]:
7
Rdy
7
PHY_AD – 5 Bit PHY Address
VALID – Data Valid from PHY (Read Only)
RDY – Data is returned from PHY (Ready Only)
6
Valid
Reserved(Default 0)
Hold time for LED signal (Default 00)
•
•
LED clock frequency (Default 0)
•
•
Reserved. Must be set to ‘0’ (Default 0)
00 = 8 msec
10 = 32 msec 11=64 msec
00 =100 M/8 = 12.5 MHz
10 = 100 M/32 = 125 MHz
5
5
4
2
4
Clock rate
PHY address
C (R/W)
01 = 16 msec
Zarlink Semiconductor Inc.
3
ZL50418
104
2
Hold Time
01 = 100 M/16 = 25 MHz
11 = 100 M/64 = 1.5625 MHz
1
0
0
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