ATXMEGA384A1-CU ATMEL [ATMEL Corporation], ATXMEGA384A1-CU Datasheet - Page 74

• Manufacturer Part Number: ATXMEGA384A1-CU
• Description: 8/16-bit XMEGA A1 Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

8067D–AVR–08/08
5. The ADC has up to ±2 LSB inaccuracy
6. TWI, a general address call will match independent of the R/W-bit value.
7. TWI, the minimum I
8. Setting HIRES PR bit makes PWM output unavailable
9. EEPROM erase and write does not work with all System Clock sources
The ADC will have up to ±2 LSB inaccuracy, visible as a saw-tooth pattern on the input volt-
age/ output value transfer function of the ADC. The inaccuracy increases with increasing
voltage reference reaching ±2 LSB with 3V reference.
Problem fix/Workaround
None, the actual ADC resolution will be reduced with up to ±2 LSB.
When the TWI is in Slave mode and a general address call is issued on the bus, the TWI
Slave will get an address match regardless of the R/W-bit (ADDR[0] bit) value in the Slave
Address Register.
Problem fix/Workaround
Use software to check the R/W-bit on general call address match.
When the TWI is in Master Read mode and issuing a Repeated Start on the bus, this will
immediately release the SCL line even if one complete SCL low period has not passed. This
means that the minimum SCL low time in the I
Problem fix/Workaround
If this causes a potential problem in the application, software must ensure that the Repeated
Start is never issued before one SCL low time has passed.
Setting the HIRES Power Reduction (PR) bit for PORTx will make any Frequency or PWM
output for the corresponding Timer/Counters (TCx0 and TCx1) unavailable on the pin.
Problem fix/Workaround
Do not write the HIRES PR bit on PORTx when frequency or PWM output from TCx0/1 is
used.
When doing EEPROM erase or Write operations with other clock sources than the 2 MHz
RCOSC, Flash will be read wrongly for one or two clock cycles at the end of the EEPROM
operation.
Problem fix/Workaround
Alt 1: Use the internal 2 MHz RCOSC when doing erase or write operations on EEPROM.
Alt 2: Ensure to be in sleep mode while completing erase or write on EEPROM. After starting
erase or write operations on EEPROM, other interrupts should be disabled and the device
put to sleep.
2
C SCL low time could be violated in Master Read mode
2
C specification could be violated.
XMEGA A1
74