S3C7044 Samsung semiconductor, S3C7044 Datasheet
S3C7044
Related parts for S3C7044
S3C7044 Summary of contents
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... S3C7044/C7048 offers an excellent design solution for a wide variety of general-purpose applications pins of the 42-pin SDIP or 44-pin QFP package can be dedicated to I/O. Seven vectored interrupts provide fast response to internal and external events. In addition, the S3C7044/C7048's advanced CMOS technology provides for low power consumption and a wide operating voltage range. PRODUCT OVERVIEW ...
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... PRODUCT OVERVIEW FEATURES SUMMARY Memory 512 4-bit RAM 4096 8-bit ROM: S3C7044 8192 8-bit ROM: S3C7048 36 I/O Pins Input only: 4 pins I/O: 24 pins N-channel open-drain I/O: 8 pins Memory-Mapped I/O Structure Data memory bank 15 8-Bit Basic Timer 4 interval timer functions Two 8-Bit Timer/Counters Programmable interval timer ...
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... S3C7044/C7048/P7048 FUNCTION OVERVIEW SAM47 CPU All S3C7-series microcontrollers have the advanced SAM47 CPU core. The SAM47 CPU can directly address up to 32K-byte of program memory. The arithmetic logic unit(ALU) performs 4-bit addition, subtraction, logical, and shift-and-rotate operations in one instruction cycle and most 8-bit arithmetic and logical operation in two cycles. ...
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... Using the BSC register, addresses and bit location can be specified sequentially using 1-bit indirect addressing instructions. In this way, a program can generate 16-bit data output by moving the bit location sequentially, incrementing or decrementing the value of the L register. You can also use direct addressing to manipulate data in the BSC. 1-4 S3C7044/C7048/P7048 bank0, bank1, and bank15. You use the ...
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... System oscillation circuit generates the internal clock signals for the CPU and peripheral hardwares. The system clock can use a crystal, ceramic oscillation source externally-generated clock signal. To drive S3C7044/C7048 using an external clock source, the external clock signal should be input and its inverted signal to X out . ...
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... When the standard oscillation stabilization interval (31 4.19 MHz) has elapsed, normal CPU operation resumes. I/O PORTS The S3C7044/C7048 has 9 I/O ports. Pin addresses for all I/O ports are mapped to locations FF0H–FFCH in bank 15 of the RAM. There are 4 input pins, 24 configurable I/O pins, and 8 software n-channel open-drain I/O pins, for a total of 36 I/O pins ...
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... COUNTER 0 8-BIT TIMER/ COUNTER 1 I/O PORT 4 P4.0–P4.3 I/O PORT 5 P5.0–P5.3 P6.0–P6.3 / I/O PORT 6 KS0–KS3 P7.0–P7.3 / I/O PORT 7 KS4–KS7 I/O PORT 8 P8.0–P8.3 Figure 1-1. S3C7044/C7048/P0408 Block Diagram TIMER RESET Xin Xout INTERRUPT CONTROL CLOCK BLOCK INTERNAL INTERRUPTS INSTRUCTION DECODER STATUS WORD ARITHMETIC AND LOGIC UNIT 512 x 4-BIT ...
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... PRODUCT OVERVIEW PIN ASSIGNMENTS P1.3/INT4 P1.2/INT2 P1.1/INT1 P1.0/INT0 P2.3/BUZ P2.2/CLO P2.1/TCLO1 P2.0/TCLO0 P0.3/BTCO P0.2/SI P0.1/SO P0.0/SCK P3.1/TCL1 P3.0/TCL0 Figure 1-2. S3C7044/C7048 Pin Assignment Diagrams (42-SDIP Pakage) 1 P8.3 13 P8.2 14 P8.1 15 P8.0 16 P3 S3C7044/C7048/P7048 P7.0/KS4 41 P7.1/KS5 40 P7.2/KS6 39 P7.3/KS7 38 P6.0/KS0 37 P6 ...
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... S3C7044/C7048/P7048 P5.3 P5.2 P5.1 P5.0 RESET X OUT P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0 Figure 1-3. S3C7044/C7048 Pin Assignment Diagrams (44-QFP Pakage S3C7044/C7048 6 (44-QFP-1010B PRODUCT OVERVIEW P8.0 31 P8.1 30 P8.2 29 P8.3 28 P0.0/SCK 27 P0.1/SO 26 P0.2/SI 25 P0.3/BTCO 24 P2.0/TCLO0 23 P2.1/TCLO1 1-9 ...
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... PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1-1. S3C7044/C7048/P0408 Pin Description Pin Name Pin Type P0.0 I/O P0.1 P0.2 P0.3 P1.0 I P1.1 P1.2 P1.3 P2.0 I/O P2.1 P2.2 P2.3 P3.0 I/O P3.1 P3.2 P3.3 P4.0–P4.3 I/O P5.0–P5.3 P6.0–P6.3 I/O P7.0–P7.3 P8.0–P8.3 I/O NOTE: Parentheses indicate pin number for 44 QFP package. 1-10 Description 4-bit I/O port. 1-bit or 4-bit read/write and test is possible. Individual pins are software configurable as input or output. ...
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... S3C7044/C7048/P7048 Table 1-1. S3C7044/C7048 Pin Descriptions (Continued) Pin Name Pin Type SCK I/O SO I/O SI I/O BTCO I/O INT0, INT1 I INT2 I INT4 I TCLO0 I/O TCLO1 I/O CLO I/O BUZ I/O TCL0 I/O TCL1 I/O KS0–KS3 I/O KS4–KS7 V – – SS RESET – in out TEST – NC – NOTE: Parentheses indicate pin number for 44 QFP package. ...
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... P8.0–P8 out RESET TEST NOTE: When pull-up resistors are provided, port 4 and port 5 pins are reset to high level; with no pull-ups, they are reset to high impedance. 1-12 Table 1-2. Overview of S3C7044/C7048 Pin Data Share Pins I/O Type I I/O I/O – I/O – I/O I/O – I/O – ...
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... S3C7044/C7048/P7048 PIN CIRCUIT DIAGRAMS Figure 1-4. Pin Circuit Type PULL-UP RESISTOR - P CHANNEL IN SCHMITT TRIGGER Figure 1-5. Pin Circuit Type A-3 - CHANNEL - CHANNEL PULL-UP RESISTOR ENABLE PRODUCT OVERVIEW V DD PULL-UP RESISTOR IN SCHMITT TRIGGER Figure 1-6. Pin Circuit Type B IN SCHMITT TRIGGER Figure 1-7. Pin Circuit Type B-4 ...
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... OUTPUT DISABLE CIRCUIT TYPE A Figure 1-9. Pin Circuit Type D 1- CHANNEL OUT - N CHANNEL V DD PULL-UP RESISTOR - P CHANNEL I/O S3C7044/C7048/P7048 V DD PULL-UP RESISTOR RESISTOR - P ENABLE DATA CIRCUIT TYPE C OUTPUT DISABLE SCHMITT TRIGGER Figure 1-10. Pin Circuit Type D-1 DATA CIRCUIT TYPE C OUTPUT DISABLE CIRCUIT TYPE A ...
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... S3C7044/C7048/P7048 DATA OUTPUT DISABLE Figure 1-12. Pin Circuit Type E-2 PRODUCT OVERVIEW VDD I/O N-CHANNEL 1-15 ...
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... S3C7044/C7048/P7048 13 ELECTRICAL DATA In this section, information on S3C7044/C7048 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: Standard Electrical Characteristics — Absolute maximum ratings — D.C. electrical characteristics — System clock oscillator characteristics — I/O capacitance — A.C. electrical characteristics — Operating voltage range Miscellaneous Timing Waveforms — ...
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... DD All I/O ports except 4 and 5 I1 – O One I/O port active OH All I/O ports active One I/O port active OL All I/O ports, total – A – stg ) are calculated as peak value OL S3C7044/C7048/P7048 Rating Units – 0 6.5 – 0 0.3 DD – 0 0.3 DD – – (Peak value) mA (note 100 (Peak value) ...
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... S3C7044/C7048/P7048 (T = – Parameter Symbol Input High V All input pins except those IH1 Voltage specified below for V V Ports and IH2 V Ports 4 and 5 with pull-up IH3 resistors assigned Ports 4 and 5 are open-drain V X IH4 IN Input Low ...
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... ± ± not include current drawn through internal pull-up resistors. DD1 DD3 S3C7044/C7048/P7048 Min Typ Max – – – – – 100 50 95 200 100 220 ...
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... S3C7044/C7048/P7048 Table 13-3. Main System Clock Oscillator Characteristics (T = – 1 5 Oscillator Clock Configuration Ceramic Xin Xout Oscillator C1 C2 Crystal Xin Xout Oscillator C1 C2 External Xin Xout Clock NOTES 1. Oscillation frequency and Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated ...
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... External SCK source Internal SCK source External SCK source Internal SCK source External SCK source Internal SCK source External SCK source Internal SCK source S3C7044/C7048/P7048 Min Typ Max – – 15 Min Typ Max 0.67 – 64 0.95 0 – 1 ...
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... S3C7044/C7048/P7048 Table 13-5. A.C. Electrical Characteristics (Continued – Parameter Symbol SI Setup Time to t SIK SCK High SI Hold Time to t KSI SCK High Output Delay for (1) t KSO SCK to SO Interrupt Input INTH INTL High, Low Width RESET Input Low ...
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... SUPPLY VOLTAGE (V) Figure 13-1. Standard Operating Voltage Range Symbol Conditions V – DDDR 1.5 V DDDR DDDR t – SREL Released by RESET t WAIT Released by interrupt S3C7044/C7048/P7048 Main Osc. Freq. ( Divided MHz 4.2 MHz 400 kHz Min Typ Max 1.5 – 5.5 – 0 – – 17 – ...
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... S3C7044/C7048/P7048 TIMING WAVEFORMS V DD EXECUTION OF STOP INSTRUCTION RESET Figure 13-2. Stop Mode Release Timing When Initiated By RESET V DD EXECUTION OF STOP INSTRUCTION POWER-DOWN MODE TERMINATING SIGNAL (INTERRUPT REQUEST) Figure 13-3. Stop Mode Release Timing When Initiated By Interrupt Request INTERNAL RESET STOP MODE DATA RETENTION MODE ...
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... ELECTRICAL DATA Timing Waveforms (continued) Figure 13-4. A.C. Timing Measurement Points (Except for X Xin TCL 13-10 V 0.8 DD MEASUREMENT POINTS V 0 Figure 13-5. Clock Timing Measurement TIL Figure 13-6. TCL Timing S3C7044/C7048/P7048 – TIH V 0 0.2 DD ...
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... S3C7044/C7048/P7048 RESET INT0 KS0 to KS7 Figure 13-8. Input Timing for External Interrupts and Quasi-Interrupts t RSL Figure 13-7. Input Timing for t INTL 0 0 ELECTRICAL DATA 0 RESET RESET Signal t INTH 13-11 ...
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... ELECTRICAL DATA SCK SI tKSO SO 13-12 tKCY tKL tKH tSIK tKSI INPUT DATA OUTPUT DATA Figure 13-9. Serial Data Transfer Timing S3C7044/C7048/P7048 0.8 VDD 0.2 VDD 0.8 VDD 0.2 VDD ...
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... S3C7044/C7048/P7048 14 MECHANICAL DATA This section contains the following information about the device package: — 42-SDIP-600 package dimensions in millimeters — 44-QFP-1010B package dimensions in millimeters #42 #1 (1.77) 0.50 ± 0.1 NOTE : Dimensions are in millimeters. #22 42-SDIP-600 #21 39.10 ± 0.2 1.778 1.00 ± 0.1 Figure 14-1. 42-SDIP-600 Package Dimensions ECHANICAL DATA 14-1 ...
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... MECHANICAL DATA #44 #1 1.00 NOTE : Dimensions are in millimeters. Figure 14-2. 44-QFP-1010B Package Dimensions 14-2 13.20 ± 0.30 10.00 ± 0.2 44-QFP-1010B + 0.10 0.35 0.80 - 0.05 S3C7044/C7048/P7048 0~8 0.1 MAX 0.0 MIN 2.05 ± 0.1 2.30 MAX ...
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... S3C7044/C7048 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The S3P7048 is fully compatible with the S3C7044/C7048, both in function and in pin configuration. Because of its simple programming requirements, the S3P7048 is ideal for use as an evaluation chip for the S3C7044/C7048 ...
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... S3P7048 OTP RESET/RESET RESET P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0 Figure 15-2. S3P7048 Pin Assignments (44-QFP Package) 15-2 P5.3 1 P5.2 2 P5 S3P7048 X 6 OUT (44-QFP-1010B NOTE: The bolds indicate an OTP pin name. S3C7044/C7048/P7048 P8.0 31 P8.1 30 P8.2 29 P8.3 28 P0.0/SCK 27 P0.1/SO 26 P0.2/SI 25 P0.3/BTCO 24 P2.0/TCLO0 23 P2.1/TCLO1 ...
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... RESET RESET NOTE means the 44-QFP OTP pin number. Table 15-2. Comparison of S3P7048 and S3C7044/C7048 Features Characteristic Program Memory Operating Voltage ( OTP Programming Mode Pin Configuration EPROM Programmability OPERATING MODE CHARACTERISTICS When 12 supplied to the V operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 15-3 below ...
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... X OUT = – 4 5 mA, Ports 4, 5 only = 2 1.6mA = 4 5 2 1.6mA = V DD LIH2 = V DD and X OUT = and X only OUT S3C7044/C7048/P7048 Min Typ Max 0 – 0 0 – 0.1 DD 0.3 V – – 0.1 V – 1.0 – ...
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... S3C7044/C7048/P7048 Table 15-4. D.C. Electrical Characteristics (Continued – Parameter Symbol Output High I V LOH Leakage Current I V Output Low LOL Leakage Current R V Pull-Up L1 Resistor Ports 0, 1 (not P1.3 Ports 4 and 5 only Pull-Down ...
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... External SCK source Internal SCK source External SCK source Internal SCK source External SCK source Internal SCK source External SCK source Internal SCK source S3C7044/C7048/P7048 Min Typ Max 0.67 – 64 0.95 0 – 1.5 1 0.48 – – 1.8 800 – ...
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... S3C7044/C7048/P7048 Table 15-5. A.C. Electrical Characteristics (Continued – Parameter Symbol t SI Setup Time to SIK SCK High t SI Hold Time to KSI SCK High (1) Output Delay for t KSO SCK Interrupt Input INTH INTL High, Low Width RESET Input Low ...
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... S3P7048 OTP CPU CLOCK 1.5 MHz 1.05 kHz 15.625 kHz CPU CLOCK = 1/n x oscillator frequency ( 64) 15 SUPPLY VOLTAGE (V) Figure 15-3. Standard Operating Voltage Range S3C7044/C7048/P7048 Main Osc. Freq. ( Divided MHz 4.2 MHz 400 kHz ...
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... S3C7044/C7048/P7048 FAIL Verify Byte Device Failed START Address= First Location V =5V, V =12. Program One 1ms Pulse Increment X YES Verify 1 Byte Last Address FAIL Compare All Byte PASS Device Passed Figure 15-4. OTP Programming Algorithm S3P7048 OTP FAIL ...