S3C72G9 Samsung semiconductor, S3C72G9 Datasheet - Page 56

• Manufacturer Part Number: S3C72G9
• Description: The S3C72G9 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core/ SAM47 (Samsung Arrangeable M
• Manufacturer: Samsung semiconductor

 


 
IRET
Operation:
Description:
Example:

SP + 1
SP + 2
SP + 3
SP + 4
SP + 5
SP + 6
SP
IRET is used at the end of an interrupt service routine. It pops the PC values successively from
the stack and restores them to the program counter. The stack pointer is incremented by six and
the PSW, enable memory bank (EMB) bit, and enable register bank (ERB) bit are also
automatically restored to their pre-interrupt values. Program execution continues from the resulting
address, which is generally the instruction immediately after the point at which the interrupt
request was detected. If a lower-level or same-level interrupt was pending when the IRET was
executed, IRET will be executed before the pending interrupt is processed.
Since the 15th bit of an interrupt start address is not loaded in the PC when the interrupt is
occured, this bit of PC values is always interpreted as a logic zero at that time. The start address
of an interrupt in the ROM must for this reason be located in 0000H-3FFFH.
The stack pointer contains the value 0FAH. An interrupt is detected in the instruction at location
0123H. RAM locations 0FDH, 0FCH, and 0FAH contain the values 2H, 3H, and 1H, respectively.
The instruction
IRET
leaves the stack pointer with the value 00H and the program returns to continue execution at
location 0123H.
During a return from interrupt, data is popped from the stack to the program counter. The data in
stack locations 0FFH-0FAH is organized as follows:
(0FAH)
(0FBH)
(0FCH)
(0FDH)
(0FEH)
(0FFH)
(00H)
Operand
Operand
-
-
IS1
C
0
Return from interrupt
1
PC14
SC2
PC11 - PC8
IS0
PC3 - PC0
PC7 - PC4
1


PC13
EMB
SC1
0
Binary Code
Operation Summary
1
PC12
ERB
SC0
0
1
0
1
PC14-8
PC7-0
PSW
SP
SP + 6
Operation Notation
(SP + 5) (SP + 4)
SP + 3) (SP + 2)
(SP + 1) (SP)
Bytes
1

 
Cycles
3