IDT72V70200PFG IDT, Integrated Device Technology Inc, IDT72V70200PFG Datasheet - Page 10

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IDT72V70200PFG

Manufacturer Part Number
IDT72V70200PFG
Description
IC DGTL SW 512X512 3.3V 100-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Type
Multiplexerr
Datasheet

Specifications of IDT72V70200PFG

Circuit
1 x 16:16
Independent Circuits
1
Voltage Supply Source
Single Supply
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output High, Low
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
72V70200PFG

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72V70200PFG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72V70200PFG
Manufacturer:
IDT
Quantity:
20 000
Part Number:
IDT72V70200PFG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
IDT72V70200 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 512 x 5
15-13
10-0
Bit
12
11
Read/Write Address:
Reset Value:
15
0
Unused
CFE
(Complete Frame Evaluation)
FD11
(Frame Delay Bit 11)
FD10-0
(Frame Delay Bits)
ST-BUS Frame
14
0
Offset Value
Offset Value
GCI Frame
FE Input
FE Input
Name
13
0
CLK
CLK
CFE
12
02
0000
12
H
,
H
.
FD11 FD10
11
0
0
When CFE = 1, the frame evaluation is completed and bits FD10 to FD0 bits contains a valid frame alignment
The falling edge of FE (or rising edge for GCI mode) is sampled during the CLK-high phase (FD11 = 1)
The binary value expressed in these bits refers to the measured input offset value. These bits are rest to
Must be zero for normal operation.
or during the CLK-low phase (FD11 = 0). This bit allows the measurement resolution to ½ CLK cycle.
zero when the SFE bit of the IMS register changes from 1 to 0. (FD10 – MSB, FD0 – LSB)
offset. This bit is reset to zero, when SFE bit in the IMS register is changed from 1 to 0.
10
1
1
Figure 4. Example for Frame Alignment Measurement
2
2
FD9
9
3
3
FD8
8
4
4
5
5
FD7
7
10
(FD[10:0] = 06
(FD11 = 0, sample at CLK LOW phase)
6
6
FD6
6
7
7
Description
8
8
H
FD5
)
(FD[10:0] = 09
(FD11 = 1, sample at CLK HIGH phase)
5
9
9
FD4
10
4
10
H
11
11
)
FD3
COMMERCIAL TEMPERATURE RANGE
3
12
12
FD2
2
13
13
14
14
FD1
5711 drw07
1
15
15
FD0
0
16

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