IDT72V70200PFG IDT, Integrated Device Technology Inc, IDT72V70200PFG Datasheet - Page 5

• Manufacturer Part Number: IDT72V70200PFG
• Description: IC DGTL SW 512X512 3.3V 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr
• Type: Multiplexerr

Specifications of IDT72V70200PFG

• Circuit: 1 x 16:16
• Independent Circuits: 1
• Voltage Supply Source: Single Supply
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output High, Low: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 72V70200PFG

to 11 of the FAR register. The SFE bit must be set to zero before a new
measurement cycle started.
is evaluated against the falling edge of the ST-BUS
the rising edge of FE is evaluated against the rising edge of the GCI frame pulse.
See Table 7 and Figure 4 for the description of the frame alignment register.
MEMORY BLOCK PROGRAMMING
connection memory block in two frames. To set bits 11 to 15 of every connection
memory location, first program the desired pattern in bits 5 to 9 of the IMS register.
program (MBP) bit of the control register high. When the block programming
enable (BPE) bit of the IMS register is set to high, the block programming data
will be loaded into the bits 11 to 15 of every connection memory location. The
other connection memory bits (bit 0 to bit 10) are loaded with zeros. When the
memory block programming is complete, the device resets the BPE bit to zero.
LOOPBACK CONTROL
the TX output data to be looped backed internally to the RX input for diagnostic
purposes.
looped back to the RX input channel (i.e., data from TX n channel m routes to
the RX n channel m internally); if the LPBK bit is low, the loopback feature is
disabled. For proper per-channel loopback operation, the contents of frame
delay offset registers must be set to zero.
streams results in a throughput delay. The device can be programmed to
perform time-slot interchange functions with different throughput delay capabili-
ties on the per-channel basis. For voice applications, variable throughput delay
is best as it ensures minimum delay between input and output data. In wideband
data applications, constant throughput delay is best as the frame integrity of the
information is maintained through the switch.
delay selected in the V/C bit of the connection memory.
VARIABLE DELAY MODE (V/C BIT = 0)
destination channels and is independent of input and output streams. The
minimum delay achievable in the IDT72V70200 is three time-slots. If the input
channel data is switched to the same output channel (channel n, frame p), it will
be output in the following frame (channel n, frame p+1). The same is true if input
channel n is switched to output channel n+1 or n+2. If the input channel n is
switched to output channel n+3, n+4,..., the new output data will appear in the
same frame. Table 1 shows the possible delays for the IDT72V70200 in the
variable delay mode.
CONSTANT DELAY MODE (V/C BIT = 1)
making use of a multiple data memory buffer. Input channel data is written into
the data memory buffers during frame n will be read out during frame n+2. In
the IDT72V70200, the minimum throughput delay achievable in the constant
IDT72V70200 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 512 x 5
In ST-BUS
The IDT72V70200 provides users with the capability of initializing the entire
The block programming mode is enabled by setting the memory block
The loopback control (LPBK) bit of each connection memory location allows
If the LPBK bit is high, the associated TX output channel data is internally
The switching of information from the input serial streams to the output serial
The delay through the device varies according to the type of throughput
In this mode, the delay is dependent only on the combination of source and
In this mode, frame integrity is maintained in all switching configurations by
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mode, the falling edge of the frame measurement signal (FE)
12
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frame pulse. In GCI mode,
5
delay mode will be one frame. For example, when input time-slot 31 is switched
to output time-slot 0. The maximum delay of 94 time-slots of delay occurs when
time-slot 0 in a frame is switched to time-slot 31 in the frame. See Table 2.
plexed or non-multiplexed bus structures. This interface is compatible with
Motorola non-multiplexed and multiplexed buses.
the device. If the IM pin is high, the device monitors the AS/ALE and DS/RD to
determine what mode the IDT72V70200 should operate in.
timing is selected. If DS/RD is high at the rising edge of AS/ALE, then the mode
2 multiplexed bus timing is selected.
address (AD0-AD7), 8-bit Data (D8-D15), Address strobe/Address latch
enable (AS/ ALE), Data strobe/Read (DS/RD), Read/Write /Write (R/W / WR),
Chip select (CS) and Data transfer acknowledge (DTA). See Figure 11 and
Figure 12 for multiplexed parallel microport timing.
data bus (AD0-AD7, D8-D15), 8-bit address bus (A0-A7) and 4 control lines
(CS, DS, R/W and DTA). See Figure 13 and 14 for Motorola non-multiplexed
microport timing.
connection and data memories. All locations provide read/write access except
for the data memory and the frame alignment register which are read only.
MEMORY MAPPING
registers and memories of the IDT72V70200.
interface mode selection (IMS), control (CR), frame alignment (FAR) and frame
input offset (FOR) registers (Table 4). If the A7 is high, A6 and A5 are low, then
A4 through A0 are used to select 32 locations corresponding to data rate of the
ST-BUS
control register allow access to the entire data and connection memories. The
control and IMS registers together control all the major functions of the device,
see Figure 3.
tions sections, after system power-up, the IMS register should be programmed
immediately to establish the desired switching configuration.
bit (MBP), the memory select bit (MS) and the stream address bits (STA). As
explained in the Memory Block Programming section, the MBP bit allows the
entire connection memory block to be programmed. The memory select bit is
used to designate the connection memory or the data Memory. The stream
address bits select internal memory subsections corresponding to input or output
serial streams.
BPD4), block programming enable bit (BPE), output stand by bit (OSB) and start
frame evaluation bit (SFE). The block programming and the block programming
enable bits allows users to program the entire connection memory (see Memory
Block Programming section). If the ODE pin is low, the OSB bit enables (if high)
or disables (if low) all ST-BUS
of the OSB bit is ignored and all TX output drivers are enabled.
The IDT72V70200 provides a parallel microprocessor interface for multi-
If the IM pin is low a Motorola non-multiplexed bus should be connected to
If DS/RD is low at the rising edge of AS/ALE, then the mode 1 multiplexed
For multiplexed operation, the required signals are the 8-bit data and
For the Motorola non-multiplexed bus, the required signals are the 16-bit
The IDT72V70200 microport provides access to the internal registers,
The address bus on the microprocessor interface selects the internal
If the A7 address input is low, then A6 through A0 are used to address the
As explained in the Serial Data Interface Timing and Switching Configura-
The data in the control register consists of the memory block programming
The data in the IMS register consists of block programming bits (BPD0-
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. The address input lines and the stream address bits (STA) of the
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output drivers. If the ODE pin is high, the contents
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