IDT72V70200PFG IDT, Integrated Device Technology Inc, IDT72V70200PFG Datasheet - Page 3

• Manufacturer Part Number: IDT72V70200PFG
• Description: IC DGTL SW 512X512 3.3V 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr
• Type: Multiplexerr

Specifications of IDT72V70200PFG

• Circuit: 1 x 16:16
• Independent Circuits: 1
• Voltage Supply Source: Single Supply
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output High, Low: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 72V70200PFG

NOTE:
1. These pins are 5V tolerant.
SYMBOL
GND
Vcc
TX0-15
RX0-15
F0i
FE
CLK
TMS
TDI
TDO
TCK
TRST
IC
RESET
A0-7
DS/RD
R/W / WR
CS
AS/ALE
IM
AD0-7
D8-15
DTA
CCO
ODE
IDT72V70200 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 512 x 5
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Ground.
Vcc
TX Output 0 to 15
(Three-state Outputs)
RX Input 0 to 15
Frame Pulse
Frame Evaluation
Clock
Test Mode Select
Test Serial Data In
Test Serial Data Out
Test Clock
Test Reset
Internal Connection
Device Reset
(Schmitt Trigger Input)
Address 0-7
Data Strobe/Read
Read/Write / Write
Chip Select
Address Strobe or
Latch Enable
CPU Interface Mode
Address/Data Bus 0 to 7 I/O
Data Bus 8-15
Data Transfer
Acknowledgment
Control Output
Output Drive Enable
NAME
12
I/O
I/O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Ground Rail.
+3.3 Volt Power Supply.
and GCI specifications.
Frame measurement input. No pull-up/down. If unused, an external pull-up or pull-down must be provided.
Serial clock for shifting data in/out on the serial streams (RX/TX 0-15). This input accepts a 4.096 MHz clock.
JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal pull-
up when not driven.
when not driven.
JTAG scan is not enabled.
Provides the clock to the JTAG test logic.
by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW, to ensure
that the IDT72V70200 is in the normal functional mode.
comply with IEEE 1114 (JTAG) boundary scan requirements.
This input (active LOW) puts the IDT72V70200 in its reset state that clears the device internal counters, registers
reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the RESET
pin must be held LOW for a minimum of 100ns to reset the device.
When non-multiplexed CPU bus operation is selected, these lines provide the A0-A7 address lines to the internal
memories.
For Motorola multiplexed bus operation, this input is DS. This active HIGH DS input works in conjunction with
CS to enable the read and write operations. For Motorola non-multiplexed CPU bus operation, this input is DS.
This active LOW input works in conjunction with CS to enable the read and write operations. For Intel multiplexed
bus operation, this input is RD. This active LOW input sets the data bus lines (AD0-7, D8-15) as outputs.
the direction of the data bus lines (AD0-7, D8-15) during a microprocessor access. For Intel multiplexed bus
operation, this input is WR. This active LOW input is used with RD to control the data bus (AD0-7) lines as inputs.
Active LOW input used by a microprocessor to activate the microprocessor port of IDT72V70200.
This input is used if multiplexed bus operation is selected via the IM input pin. For Motorola non-multiplexed
port is in non-multiplexed mode.
are also the input address bits of the microprocessor port.
pull-up resistor is required to hold a HIGH level when the pin is in high-impedance.
the CCO bit in the connection memory. See External Drive Control Section.
This is the output enable control for the TX0 to TX15 serial outputs. When ODE input is LOW and the OSB
bit of the IMS register is LOW, TX0-15 are in a high-impedance state. If this input is HIGH, the TX0-15
output drivers are enabled. However, each channel may still be put into a high-impedance state by using the
per channel control bit in the connection memory.
Serial data output stream. These streams have a data rate of 2.048 Mb/s.
Serial data input stream. These streams have a data rate of 2.048 Mb/s.
This input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS
JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up
JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state when
In the cases of Motorola non-multiplexed and multiplexed bus operations, this input is R/W. This input controls
When IM is HIGH, the microprocessor port is in the multiplexed mode. When IM is LOW, the microprocessor
These pins are the eight least significant data bits of the microprocessor port. In multiplexed mode, these pins
These pins are the eight most significant data bits of the microprocessor port.
This active LOW output signal indicates that a data bus transfer is complete. When the bus cycle ends, this pin
drives HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A
This is a 4.096 Mb/s output containing 512 bits per frame respectively. The level of each bit is determined by
Connect to GND for normal operation. This pin must be LOW for the IDT72V70200 to function normally and to
Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-reset state. This pin is pulled
and brings TX0-15 and microport data outputs to a high-impedance state. The time constant for a power up
bus operation, connect this pin to ground.
3
DESCRIPTION
COMMERCIAL TEMPERATURE RANGE
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