PC87200VUL160A NSC [National Semiconductor], PC87200VUL160A Datasheet - Page 17

• Manufacturer Part Number: PC87200VUL160A
• Description: PC87200 PCI to ISA Bridge
• Manufacturer: NSC [National Semiconductor]

7.0 Register Descriptions
7.2 Chipset Register Space
The Chipset Register Space of the PC87200 is comprised
of one function with PCI header registers. There is no
memory or I/O mapped register.
7.2.1 Bridge Configuration Registers - Function 0
The register space designated as Function 0 (F0) contains
registers used to configure features and functionality
Index 00h-01h
Index 02h-03h
Index 04h-05h
Index 06h-07h
15:10
10:9
Bit
15
14
13
12
11
9
8
7
6
5
4
3
2
1
0
Reserved — Set to 0.
Fast Back-to-Back Enable (Read Only) — This function is not supported when PC87200 is a master. It is al-
ways disabled (must always be set to 0).
SERR# — Allow SERR# assertion on detection of special errors: 0 = Disable; 1 = Enable.
Wait Cycle Control (Read Only) — This function is not supported in PC87200. It is always disabled (bit is set
to 0).
Parity Error — Allow PC87200 to check for parity errors on PCI cycles for which it is a target, and to assert
PERR# when a parity error is detected: 0 = Disable; 1 = Enable.
VGA Palette Snoop Enable (Read Only) — This function is not supported in PC87200. It is always disabled
(bit is set to 0).
Memory Write and Invalidate —
cache line register is set to 16 bytes (04h). 0=Disable, 1=Enable.
Special Cycles — This function is not supported. It must always be set to 0.
Bus Master — Allow PC87200 bus mastering capabilities: 0 = Disable; 1 = Enable. Set this bit to 1.
Memory Space — Allow PC87200 to respond to memory cycles from the PCI bus: 0 = Disable; 1 = Enable.
PC87200 will only respond to memory cycles destined for the ISA bus as none of its internal functions are
memory-mapped.
I/O Space — Allow PC87200 to respond to I/O cycles from the PCI bus: 0 = Disable; 1 = Enable.
Detected Parity Error — This bit is set whenever a parity error is detected. Write 1 to clear.
Signaled System Error — This bit is set whenever PC87200 asserts SERR# active. Write 1 to clear.
Received Master Abort — This bit is set whenever a master abort cycle occurs. A master abort will occur
when a PCI cycle is not claimed, except for special cycles. Write 1 to clear. Register is cleared after RMA is
read.
Received Target Abort — This bit is set whenever a target abort is received while the PC87200 is the master
for the PCI cycle. Write 1 to clear.
Signaled Target Abort — This bit is set whenever the PC87200 signals a target abort. This occurs when an
address parity error occurs for an address that hits in the active address decode space of the PC87200. Write
1 to clear.
DEVSEL# Timing — These bits are always 01, as the PC87200 will always respond to cycles for which it is
an active target with medium DEVSEL# timing.
00 = Fast
01 = Medium
10 = Slow
11 = Reserved
(Continued)
Table 4. Bridge Configuration Registers
Vendor Identification Register (RO)
Device Identification Register (RO)
PCI Command Register (R/W)
Allow PC87200 to do memory write and invalidate cycles, if the PCI
PCI Status Register (R/W)
17
Description
unique to the PC87200. All registers in Function 0 are
directly accessed (i.e., there are no memory or I/O mapped
registers in F0). Table 4 gives the bit formats for these reg-
isters.
IMPORTANT: Register bits marked internal use should
not be overwritten, else error will occur .
Reset Value = 100Bh
Reset Value = 0107h
Reset Value = 0280h
Reset Value =0021h
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