PC87200VUL160A NSC [National Semiconductor], PC87200VUL160A Datasheet - Page 3

• Manufacturer Part Number: PC87200VUL160A
• Description: PC87200 PCI to ISA Bridge
• Manufacturer: NSC [National Semiconductor]

3.0 Device Overview
The PC87200 can be described as providing the functional
blocks shown in Figure 1.
— PCI bus master/slave interface
— ISA bus master/slave interface
— Serial IRQ slave mode interface
— PROHIBIT signal support
— PC/PCI DMA interface
3.1 PCI Bus Interface
The PC87200 provides a PCI bus interface that is both a
slave for PCI cycles initiated by the CPU or other PCI mas-
3.2 ISA Bus Interface
The PC87200 provides an ISA bus interface for subtrac-
tive-decoded memory and I/O cycles on PCI. The
PC87200 is the default subtractive decoding agent and will
forward all unclaimed memory and I/O cycles to the ISA
interface; however, the PC87200 may be configured to
ignore either I/O, memory or all unclaimed cycles (subtrac-
tive decode disabled) by asserting the PROHIBIT signal.
ISA master cycles will only be passed to the PCI bus if they
access memory. I/O accesses are left to complete on the
ISA bus.
ISA master cycles that access memory on ISA bus are not
supported by the PC87200.
3.3 Serialized IRQ support
The PC87200’s Serial Interrupt interface uses a serial
interrupt bus to transmit ISA Bus legacy interrupt requests.
The bus is a one pin bus (SERIRQ) and uses the PCI clock
as its timing reference. The serial interrupt bus is a multi-
drop bus that is shared by all PCI devices that have legacy
interrupts. The serial interrupt logic conforms to the serial-
Serialized IRQ
Interface
Serial IRQ Slave
mode interface logic
ISA bus Target
Interface
PCI to X-Bus / X-Bus to PCI Bridge
Internal Block Diagram
ISA Bus
X-Bus
PCI Bus
3
ter devices, and a PC/PCI DMA master for DMA transfer
cycles. The PC87200 supports positive decode for the
BIOS ROM in the special test mode and implements sub-
tractive decode for unclaimed PCI accesses when the
PROHIBIT signal is low. The PC87200 also generates
address and data parity and performs parity checking.
Configuration registers are accessed through the PCI inter-
face using the PCI Bus Type 1 configuration mechanism as
described in the PCI 2.1 Specification.
ized IRQ defined in the Serialized IRQ on the “PCI way” -
Version 6.0 specification. Programming of the serial inter-
rupt controller when the controller is currently running can
produce unexpected results.
ISA bus Master
Interface
PC/PCI DMA
PCI Configuration
PC87200 Support
Decoding logic
Interface
X-Bus Arbiter
Registers
www.national.com
PCPCIREQ#
PCPCIGNT#
PROHIBIT
BPD#