AM85C30-10 AMD [Advanced Micro Devices], AM85C30-10 Datasheet - Page 7

• Manufacturer Part Number: AM85C30-10
• Description: Enhanced Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

PIN DESCRIPTION
Bus Timing and Reset
RD
Read (Input; Active Low)
This signal indicates a Read operation and, when the
SCC is selected, enables the SCC’s bus drivers. During
the Interrupt Acknowledge cycle, this signal gates the
interrupt vector onto the bus if the SCC is the highest pri-
ority device requesting an interrupt.
WR
Write (Input; Active Low)
When the SCC is selected, this signal indicates a Write
operation. The coincidence of RD and WR is interpreted
as a reset.
Channel Clocks
RTxCA, RTxCB
Receive/Transmit Clocks (Inputs; Active Low)
These pins can be programmed in several different
modes of operation. In each channel, RTxC may supply
the receive clock, the transmit clock, the clock for the
baud rate generator, or the clock of the digital phase-
locked loop. These pins can also be programmed for
use with the respective SYNC pins as a crystal oscilla-
tor. The receive clock may be 1, 16, 32, or 64 times the
data rate in asynchronous modes.
TRxCA, TRxCB
Transmit/Receive Clocks
(Inputs/Outputs; Active Low)
These pins can be programmed in several different
modes of operation. TRxC may supply the receive clock
or the transmit clock in the input mode or supply the out-
put of the digital phase-locked loop, the crystal oscilla-
tor, the baud rate generator, or the transmit clock in the
output mode.
Channel Controls for Modem, DMA,
or Other
CTSA, CTSB
Clear to Send (Inputs; Active Low)
If these pins are programmed as Auto Enables, a Low
on these inputs enables their respective transmitters. If
not programmed as Auto Enables, they may be used as
general-purpose inputs. Both inputs are Schmitt-trigger
buffered to accommodate slow rise-time inputs. The
SCC detects pulses on these inputs and may interrupt
the CPU on both logic level transitions.
DCDA, DCDB
Data Carrier Detect (Inputs; Active Low)
These pins function as receiver enables if they are pro-
grammed as Auto Enables; otherwise, they may be
Am85C30
used as general-purpose input pins. Both are Schmitt-
trigger buffered to accommodate slow rise-time signals.
The SCC detects pulses on these pins and may interrupt
the CPU on both logic level transitions.
DTR/REQA, DTR/REQB
Data Terminal Ready/Request
(Outputs; Active Low)
These outputs follow the inverted state programmed
into the DTR bit in WR5. They can also be used as
general-purpose outputs or as Request Lines for a DMA
controller.
RTSA, RTSB
Request to Send (Outputs; Active Low)
When the Request to Send (RTS) bit in Write Register 5
is set, the RTS signal goes Low. When the RTS bit is re-
set in the asynchronous mode and Auto Enable is on,
the signal goes High after the transmitter is empty. In
SYNC mode, or in asynchronous mode with Auto En-
able off, the RTS pins strictly follow the inverted state of
the RTS bit. Both pins can be used as general-purpose
outputs.
In SDLC mode, the AUTO RTS RESET enhancement
described later in this document brings RTS High after
the last 0 of the closing flag leaves the TxD pin.
SYNCA, SYNCB
Synchronization (Inputs/Outputs; Active Low)
These pins can act either as inputs, outputs, or part of
the crystal oscillator circuit. In the Asynchronous Re-
ceive mode (crystal oscillator option not selected), these
pins are inputs similar to CTS and DCD. In this mode,
transitions on these lines affect the state of the Sync/
Hunt status bits in Read Register 0 but have no other
function.
In External Synchronization mode with the crystal
oscillator not selected, these lines also act as inputs.
In this mode, SYNC must be driven Low two receive
clock cycles after the last bit in the SYNC character is
received. Character assembly begins on the rising edge
of the receive clock immediately preceding the activa-
tion of SYNC.
In the Internal Synchronization mode (Monosync and
Bisync) with the crystal oscillator not selected, these
pins act as outputs and are active only during the part of
the receive clock cycle in which SYNC characters are
recognized. The SYNC condition is not latched, so
these outputs are active each time a SYNC pattern is
recognized (regardless of character boundaries). In
SDLC mode, these pins act as outputs and are valid on
receipt of a flag.
AMD
7