HI-3282CDI-10 HOLTIC [Holt Integrated Circuits], HI-3282CDI-10 Datasheet
HI-3282CDI-10
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HI-3282CDI-10 Summary of contents
Page 1
... DO-160D, Level 3. The transmitter section provides the ARINC 429 communication protocol. external ARINC 429 Line Driver such as the Holt HI-3182 or HI-8585 is required to translate the 5 volt logic outputs to ARINC 429 drive levels. The 16-bit parallel data bus exchanges the 32-bit ARINC data word in two steps when either loading the transmitter or interrogating the receivers ...
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... Latch enable for byte 1 entered from data bus to transmitter FIFO. Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high after transmission and FIFO empty. "ONES" data output from transmitter. ...
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... FUNCTIONAL DESCRIPTION CONTROL WORD REGISTER The HI-3282 contains 11 data flip flops whose D inputs are con- nected to the data bus and clocks connected to flip flop provides options to the user as follows: DATA BUS FUNCTION CONTROL PIN BD04 PAREN Enables parity bit insertion into ...
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... Kohm resistors, they are just below the standard 6.5 V minimum ARINC data threshold and just above the 2.5 V maximum ARINC null threshold. The receivers of the HI-3282-10 when used with external 10 Kohm resistors will withstand DO-160D, Level 3, waveforms 3, 4 and 5A. No additional lightning protection circuit is necessary. ...
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... TRANSMITTER PARITY Control register bit BD04 (PAREN) enables parity bit insertion into transmitter data bit 32. Parity is always inserted if DBCEN is open or high. If DBCEN is low, logic 0 on PAREN inserts data on bit 32, and logic 1 on PAREN inserts parity on bit 32. DBCEN CONTROL REGISTER BD04, BD12 ...
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... SEL input. During repeater operation however, the lower byte of the data word must be read first. This is necessary because, as the data is being read also being loaded into the FIFO and the transmitter FIFO is always EN, the byte loaded with the lower byte of the data word first ...
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... ENDAT 429DO or 429DO 429DI BIT 32 D D/R D/REN EN t SELEN SEL DON'T CARE t ENPL PL1 PL2 TX/R ENTX 429DO HI-3282 TRANSMITTER OPERATION BYTE 1 VALID t DWSET t DWHLD PL12 TRANSMITTING DATA ARINC BIT DATA DATA BIT 1 BIT 2 REPEATER OPERATION TIMING t END ENEN ...
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... Input Source I IL Differential GND Vcc C H Input Voltage Input Voltage Input Sink I IH Input Source I IL Input Voltage Input Voltage Input Sink I IH Input Source I IL DCBEN Pin Output Sink ...
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... Setup - DATA BUS Valid to Hold - Delay - TRANSMISSION TIMING Spacing - Delay - ENTX HIGH to 429DO or Delay - ENTX HIGH to 429DO or Delay - 32nd ARINC Bit to TX/R HIGH Spacing - TX/R HIGH to ENTX L0W REPEATER OPERATION TIMING Delay - TX/R LOW to ENTX HIGH Master Reset Pulse Width ARINC Data Rate and Bit Timing HI-3282 ...
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... ADDITIONAL HI-3282 PIN CONFIGURATIONS PIN CONFIGURATION (REC. 1 INPUT) 429DI1(A) (REC.1 INPUT) 429DI1(B) (REC. 2 INPUT) 429DI2(A) (REC. 2 INPUT) 429DI2(B) ( REC.1 DATA FLAG D/R1 ( REC.2 DATA FLAG D/R2 (REC. BYTE SELECT) ( REC. 1 OUTPUT ENABLE ( REC. 2 OUTPUT ENABLE HI-3282CDI-10 / HI-3282CDT-10 / HI-3282CDM-10 N/C 7 D/R1 8 D/R2 9 SEL 10 EN1 11 EN2 12 BD15 13 BD14 14 BD13 15 BD12 16 ...
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... TO +85° -55°C TO +125° -55°C TO +125°C M PACKAGE DESCRIPTION CD 40 PIN CERAMIC SIDE BRAZED DIP 44 PIN CERAMIC LEADLESS CHIP CARRIER CL INPUT SERIES RESISTANCE BUILT-IN REQUIRED EXTERNALLY 35 Kohm 25 Kohm -10 (Note 1) LEAD FINISH Blank Tin / Lead (Sn / Pb) Solder ...
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... PIN NO. 1 .045 x 45° .690 ± .005 (17.526 ± .127) SQ. .172 ± .008 (4.369 ± .203) (15.494± .508) HI-3282 PACKAGE DIMENSIONS 2.020 MAX (51.308 MAX) .050 TYP (1.270 TYP) .085 ± .009 (2.159 ± .229) .018 TYP .100 BSC ( ...
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... PLASTIC QUAD FLAT PACK (PQFP) .547 ± .010 (13.90 ± .25) SQ. See Detail A .097 MAX. (2.45) 44-PIN CERAMIC LEADLESS CHIP CARRIER .020 INDEX (.508 INDEX) PIN 1 .651 ± .011 (16.535 ± .279) SQ. HI-3282 PACKAGE DIMENSIONS .394 ± .004 (10.0 ± .10) SQ. .079 +.004 / -.006 (2 ...