HI-3282CDI-10 HOLTIC [Holt Integrated Circuits], HI-3282CDI-10 Datasheet - Page 5

• Manufacturer Part Number: HI-3282CDI-10
• Description: ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER
• Manufacturer: HOLTIC [Holt Integrated Circuits]

FUNCTIONAL DESCRIPTION (cont.)
TRANSMITTER
A block diagram of the transmitter section is shown in Figure 3.
FIFO OPERATION
The FIFO is loaded sequentially by first pulsing
and then
the 31 bit word in the next available position of the FIFO. If TX/R,
the transmitter ready flag, is high (FIFO empty), then 8 words,
each 31 bits long, may be loaded. If TX/R is low, then only the
available positions may be loaded. If all 8 positions are full, the
FIFO ignores further attempts to load data.
DATA TRANSMISSION
When ENTX goes high, enabling transmission, the FIFO
positions are incremented with the top register loading into the
data transmission shift register. Within 2.5 data clocks the first
data bit appears at either 429DO or
data transmission shift register are presented sequentially to the
outputs in the ARINC 429 format with the following timing:
The word counter detects when all loaded positions are
transmitted and sets the transmitter ready flag, TX/R, high.
TRANSMITTER PARITY
Control register bit BD04 (PAREN) enables parity bit insertion into
transmitter data bit 32. Parity is always inserted if DBCEN is open
or high. If DBCEN is low, logic 0 on PAREN inserts data on bit 32,
and logic 1 on PAREN inserts parity on bit 32.
ARINC DATA BIT TIME
WORD GAP TIME
PL2
DATA BIT TIME
NULL BIT TIME
to load byte 2. The control logic automatically loads
LOAD SHIFT REGISTER
31 BIT PARALLEL
8 X 31 FIFO
DATA BUS
FIGURE 3.
HIGH SPEED
10 Clocks
40 Clocks
5 Clocks
5 Clocks
TRANSMITTER BLOCK DIAGRAM
429DO
CONTROL REGISTER BD04, BD12
DBCEN
. The 31 bits in the
PL1
LOW SPEED
320 Clocks
80 Clocks
40 Clocks
40 Clocks
ADDRESS
to load byte 1
LOAD
BIT CLOCK
HOLT INTEGRATED CIRCUITS
WORD CLOCK
HI-3282
GENERATOR
PARITY
The parity generator counts the ONES in the 31-bit word. If the BD12
control word bit is set low, the 32nd bit transmitted will make parity
odd. If the control bit is high, the parity is even.
SELF TEST
If the BD05 control word bit is set low, 429DO or
connected to the receivers inputs, bypassing the interface circuitry.
Data to Receiver 1 is as transmitted and data to Recevier 2 is the
complement. 429DO and
test.
SYSTEM OPERATION
The two receivers are independent of the transmitter. Therefore,
control of data exchanges is strictly at the option of the user. The only
restrictions are:
MASTER RESET (
On a Master Reset data transmission and reception are immedi-
ately terminated, the transmit FIFO and receivers cleared as are
the transmit and receive flags. The Control Register is not affected
by a Master Reset.
5
1. The received data may be overwritten if not retrieved within
one ARINC word cycle.
2. The FIFO can store 8 words maximum and ignores attempts
3. Byte 1 of the transmitter data must be loaded first.
4. Either byte of the received data may be retrieved first. Both
bytes must be retrieved to clear the data ready flag.
5. After ENTX, transmission enable, goes high it cannot go low
until TX/R, transmitter ready flag, goes high. Otherwise, one
ARINC word is lost during transmission.
CLOCK
to load addition data if full.
DATA
WORD COUNTER
CONTROL REGISTER
FIFO CONTROL
DATA CLOCK
SEQUENCER
WORD GAP
COUNTER
LOADING
DIVIDER
NULL TIMER
SEQUENCER
BIT BD13
DATA AND
MR
AND
FIFO
AND
BIT
)
SEQUENCE
WORD COUNT
INCREMENT
429DO
START
outputs remain active during self
429DO
TX CLK
CLK
429DO
TX/R
ENTX
PL1
PL2
429DO
are internally