HI-3717PCI HOLTIC [Holt Integrated Circuits], HI-3717PCI Datasheet

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... SYNC0 - 10 SYNC1 - Pin Plastic Quad Flat Pack (PQFP) HOLT INTEGRATED CIRCUITS www.holtic.com HI-3717 with SPI Interface (Top View OUTHA 32 - TXOUTHA 31 - TXOUTHB 30 - OUTHB HI-3717PCI 29 - TXHB HI-3717PCT 28 - TXBA 27 - OUTBA HI-3717PCM 26 - TXOUTBA 25 - TXOUTBB 24 - OUTBB 23 - TXBB 44 - Pin Plastic 7mm x 7mm Chip-Scale Package (QFN OUTHA ...

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... SI SO ARINC 717 ACLK Clock Divider RSEL HBP Line Receiver RINA 40 KΩ RINB 40 KΩ RINA-40 RINB-40 BPRZ Line Receiver HI-3717 VDD HBP Rate Encoder Slew Rate & Loopback Test Control BPRZ Encoder Transmit FIFO Status Register TXFSTAT Control Control ...

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... Frame Count Utility Register, WRDCNT. Output is user programmable to indicate the Receive FIFO Full, Half-full or Empty RFIFO OUTPUT state. See FSPIN<7:6> in Table 7, FIFO Status Pin Assignment Register. Receive FIFO Overflow. Output goes high when an attempt is made to load a full ROVF OUTPUT Receive FIFO INPUT ...

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... When CS goes low, the next 8 clocks at the SCK pin shift an instruction op code into the decoder, starting with the first rising edge. The op code is shifted into the SI pin, most significant bit (MSB) first. The SPI can be clocked up to10 MHz. The SPI instructions are of a common format. The most significant bit (MSB) specifies whether the instruction is a write “ ...

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... The instruction op code is immediately followed by a data byte comprising the 8-bit data word read or written. For a register read or write negated after the data byte is transferred. Table 2 summarizes the HI-3717 SPI instruction set SCK ...

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... R/W 0 Setting this bit overrides the state of BR2:0 and sets the data rate at 384 Bits/sec. (32 words/sec.) 2-1 SLEW1:0 R/W 0 Setting these bits controls the nominal slew rate on both the HBP & BPRZ transmit channel outputs ...

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... TEST R/W 0 Test Mode - A “1” in this bit position will disable the line receiver and both line drivers and the digital transmitted data will be looped back to the HBP or BPRZ data sampler selected by RXSEL . RECEIVE FIFO STATUS REGISTER: RXFSTAT Read: SPI Op-code 0xE6 ...

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... REGISTER: FSPIN Read: SPI Op-code 0xEA Write: SPI Op-code 0x6A Bit Name R/W Default Description RFIFO1:0 R/W 0 These bits program which Receive FIFO Status Register bit is represented by the RFIFO pin . TFIFO R/W 0 The bit programs which Transmit FIFO Status Register bit is represented by the TFIFO pin. ...

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... The first 12- bit word of a subframe that appears on the ARINC 717 bus is the synchronization code with the least significant bit (LSB) first. This is immediately followed 8191 12-bit data words, all within1 second from the start of the synchronization code. The next three subframes immediately follow the first subframe with their synchronization code as the first 12-bit word of the subframe followed by the same number of data words as the first subframe ...

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... MR pin. A software reset is also possible via the SPI communications interface by writing a “1” to the CTRL1<3>. This bit places both the Receive and Transmit FIFO’s in the empty state, clears the sync detection logic, and sets both the HBP and BPRZ line drivers to a high impedance state. All other registers remain unchanged. The device is held in the reset state until a “ ...

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... No Sync Detect Mode In this mode, the INSYNC is set to “1” and all data is stored in the Receive FIFO. Without sync detection, the Receive FIFO just records the sequential bits, not words, from the bus the user to detect the sync marks and determine the word boundaries in this mode ...

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... When the signal is outside the differential voltage ranges defined for all the shift registers, a “0” is clocked into all three registers. Only one shift register can clock “1” for a given sample. The Null shift register is only used for the BPNZ format. DIFFERENTIAL ...

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... ARINC 717 word in the four remaining bit locations of what are normally part of an op-code. The remaining 8-bits of the ARINC 717 word are in a normal SPI data byte. This method use one less SPI data byte than a normal read instruction ARINC 717 words may be held in the Receive FIFO. The RFFULL bit (RXFSTAT< ...

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... The SPI format for writing an ARINC 717 word and Fast Word to the HI-3717 Transmit FIFO is the same as the read format, except the 12 BIT PARALLEL LOAD SHIFT REGISTER 32 word x 12 bit FIFO ...

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... Software Reset A software reset is also possible via the SPI communications in- terface by writing a “1” to the CTRL1<3>. This bit places both the Receive and Transmit FIFO’s in the empty state, clears the sync detection logic, sets both the HBP and BPRZ line drivers to a high impedance state and disables the input sampling of both analog line receivers ...

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... TIMING DIAGRAMS CS t CHH SCK SCKH SCKL SCK SO Hi Impedance HBP DATA BPRZ DATA INSYNC RFIFO (RFEMPTY) RFIFO (RFFULL) ROVF 2nd to LAST WORD Bit 10 Bit 11 HBP DATA BPRZ DATA t TEMPTY TEMPTY FIGURE 13. Transmit FIFO Empty Flag Timing HI-3717 ...

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... FIGURE 15. Bi-Polar Return to Zero (BPRZ) Output Waveforms HARVARD BI-PHASE (HBP) TXHA t TXHB BI-POLAR RETURN ZERO (BPRZ) TXBA t TXBB one level FIGURE 16. Harvard Bi-Phase (HBP) & Bi-Polar Return to Zero (BPRZ) Logic Output Waveforms HI-3717 HBP BIT HBP BIT Data Bit 0 Data Bit 1 +5V + ...

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... Input Sink I IH Input Source I IL Differential C (RINA to RINB GND Input Voltage Input Sink I IH Input Source HOLT INTEGRATED CIRCUITS 18 (Hi-Temp): ..... -55°C to +125°C LIMITS UNIT MIN TYP MAX 2.0 5.0 8.0 V -8.0 -5.0 -2.0. V 3.5 5.0 6.5 V -1.5 0 +1.5 V -1.5 0 +1.5 V 3.5 5.0 6.5 V 6.5 10.0 13.0 V -13 ...

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... Transmitting Data at 8192 words/sec. Transmitting Data in 8192 words/sec. HI-3717 SYMBOL CONDITIONS HI V 600 ohm load OHH LO V OLH HI V 600 ohm load OHHA LO V OLHA HI V OHHB LO V OLHB ONE V No load OHB ZERO V OLB NULL V ONUL ONE V No load OHBA ...

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... Delay - RFFULL high to ROVF high (plus 12 data bits) TRANSMITTER TIMING TFEMPY flag high to beginningt of first data bit of last word in Transmit FIFO Line driver transition differential times (Both the Harvard Bi-Phase and Bi-Polar Return to Zero are set to the same slew rate) CNTL0<2:1> CNTL0< ...

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... HEAT SINK - CHIP-SCALE PACKAGE ONLY The HI-3717PCx uses a 44-pin plastic chip-scale package. This package has a metal heat sink pad on its bottom surface. This heat sink is electrically isolated from the die. ORDERING INFORMATION HI - 3717 PART NUMBER PART NUMBER PART NUMBER HI-3717 To enhance thermal dissipation, the heat sink can be soldered to matching circuit board pad ...

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... REVISION HISTORY P/N Rev Date Description of Change DS3717 NEW 08/11/11 Initial Release DS3717 A 08/23/11 Corrected typographical errors. Deleted QFN power dissipation reference. Ds3717 B 11/4/11 Updated SPI to 10MHz, added I limits, corrected example typographical error. HI-3717 DD HOLT INTEGRATED CIRCUITS 22 ...

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... PLASTIC CHIP-SCALE PACKAGE (QFN) .276 BSC (7.00) .276 Top View BSC (7.00) .039 max (1.00) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) 44-PIN PLASTIC QUAD FLAT PACK (PQFP) .547 ± .010 (13.90 ± .25) SQ. See Detail A ...