HI-3717PCI HOLTIC [Holt Integrated Circuits], HI-3717PCI Datasheet - Page 13

• Manufacturer Part Number: HI-3717PCI
• Description: Single-Rail ARINC 717 Protocol IC with SPI Interface
• Manufacturer: HOLTIC [Holt Integrated Circuits]

FUNCTIONAL DESCRIPTION (cont.)
There are also two bits in the Receive FIFO Status Register,
RXFSTAT<6:5> that provide a realtime indicator when each of the
four ARINC 717 subframe sync marks are received. The bits are
valid only when INSYNC is “1” and are updated when the subframe
sync word is loaded into the Receive FIFO.
The final mode is No Synchronization, CRTL1<1> = “1”. In this
mode data is captured and loaded directly to the Receive FIFO in
the order it was received. It is the responsibility of the user to extract
the data from the FIFO and determine word, frame and subframe
boundaries. The INSYNC bit remains “0” while in this mode.
Receive FIFO and Retrieving Data
Data is transferred from the Receive FIFO starting with the valid
subframe sync mark when INSYNC was set to “1” and continues
with each consecutive 12-bit word until INSYNC is set to “0”.
Each time a valid ARINC 717 word is loaded to the Receive FIFO
the RFFULL, RFHALF and RFEMPTY bits in the Receive FIFO
Status Register (RXFSTAT<4:2>) are updated. Each word is
retrieved from the Receive FIFO via the SPI interface using SPI
Op-code instruction 0xF6 (word only), 0xFE (word & word count) or
0xC (Fast Read).
The SPI read instruction 0xF6 format is an 8-bit op-code followed by
two 8-bit data words. The four most significant bits (MSB) of the first
data word are always “0” followed by the first four MSB of the ARINC
717 word. The second data word contains the remaining 8-bits of
the ARINC 717 word. The least significant bit (LSB) of the ARINC
717 word is the LSB of the second 8-bit data word.
The format for read word and word count instruction 0xFE is the
same as the read instruction with the addition of two additional 8-bit
data bytes that contain the word count and the corresponding sync
subframe information. The third 8-bit SPI data byte contains the 8
MSB bits of the word count. The fourth data byte is comprised of
remaining 5 bits of the word count as well as the two bit code for the
subframe number in the same format as described in the RFXSTAT
Register Description. Refer to Example 5 in Figure 5 for more
details on the format for this instruction.
ZEROS
ACLK
RSEL
ONES
NULL
CTRL0<6:4>
SHIFT REGISTER
SHIFT REGISTER
SHIFT REGISTER
DATA CLOCK
DIVIDER
FIGURE 8.
HOLT INTEGRATED CIRCUITS
DECODER
DECODER
CTRL0<0>
BPRZ
HBP
ARINC 717 Receiver Block Diagram
HI-3717
HBP / BPRZ
SELECT
13
The Fast Read instruction 0xC uses only one SPI data byte for a
read operation. This is accomplished by using only first four bits for
the SPI op-code and placing the first four most significant bits of the
ARINC 717 word in the four remaining bit locations of what are
normally part of an op-code. The remaining 8-bits of the ARINC 717
word are in a normal SPI data byte. This method use one less SPI
data byte than a normal read instruction.
Up to 32 ARINC 717 words may be held in the Receive FIFO. The
RFFULL bit (RXFSTAT<4>) is set to “1” when the Receive FIFO is
full. Failure to unload the Receive FIFO when full will result in loss of
new data words until there are less than 32 words in the FIFO. The
RFOVF bit (RXFSTAT<1>) and external FROV pin are set to “1”
when an attempt is made to write to a full Receive FIFO.
The Receive FIFO half-full flag, the RFHALF bit (RXFSTAT<3), is
set to “1” whenever the Receive FIFO contains exactly 16 words.
The RFHALF bit provides a useful indicator to the host CPU that the
FIFO is filling up.
The Receive FIFO empty, the RFEMPTY bit (RXFSTAT<2>), is set
to “1” when the Receive FIFO is empty. It is reset to “0” when there
is at least one word in the Receive FIFO.
When the HI-3717 attempts to load a valid word to a full Receive
FIF0, the RFOVF flag, RXFSTAT<1>, and the external RFOV pin
are set to “1”. The Receive FIFO ignores any attempt to load any
additional words if it is full. The RFOVF flag and RFOV pin are reset
to “0” when either the INSYNC goes to “0” or the device is reset.
The external RFIFO pin is programmable in the FIFO Status Pin
Assignment Register (FSPIN<7:6>) to reflect the value of the
RFFULL, RFHALF or the RFEMPTY status bit. Refer to the FSPIN
Register Description for the bit values that assign the RFFULL,
RFHALF or RFEMPTY status bit to the RFIFO pin. The default
state is assignment of the RFEMPTY bit to the RFIFO pin.
Word Count Utility Register, WRDCNT, is used to cause the external
MATCH pin to be set to”1” when a specific word count is reached in a
specific subframe. WRDCNT<15:3> specifies the location in the
subframe and WRDCNT<1:0> specifies the subframe that is
monitored. MATCH is “1” until the next word is loaded into the
Receive FIFO.
The Match word and subframe bit assignments of the Word Count
Utility Register, WRDCNT, are found in Table 8.
12-BIT COMPARATOR
SYNC DETECTION
12-BIT SERIAL
WORD COUNT
SUBFRAME
DETECTION
REGISTER
&
CLOCK
WORD
32 WORD x 12-BIT
INPUT REGISTER
INPUT REGISTER
12-BIT SERIAL
12-BIT SERIAL
RECEIVE FIFO
to Line Drivers
INSYNC
RFIFO
ROVF
SYNC0
SYNC1