AT52BR3224A-70CI ATMEL [ATMEL Corporation], AT52BR3224A-70CI Datasheet
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AT52BR3224A-70CI
Related parts for AT52BR3224A-70CI
AT52BR3224A-70CI Summary of contents
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... AT52BR3224A Bottom AT52BR3224AT Top AT52BR3228A Bottom AT52BR3228AT Top Flash Plane SRAM Architecture Configuration 32M 256K x 16 32M 256K x 16 32M 512K x 16 32M 512K x 16 32-megabit Flash + 4-megabit/ 8-megabit SRAM Stack Memory AT52BR3224A AT52BR3224AT AT52BR3228A AT52BR3228AT Preliminary Rev. 3338B–STKD–6/03 1 ...
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... SUB SVCC SGND SCS1 SCS2 SWE SOE AT52BR3224A(T)/ AT52BR3228A(T) (Top View) AT52BR3224A(T)/3228A(T) 2 Function Flash/SRAM Common Address Input for 4M SRAM Flash/SRAM Common Address Input for 8M SRAM Flash Address Input Flash Chip Enable Flash Output Enable Flash Write Enablee Flash Reset Flash READY/BUSY Output ...
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... Block Diagram Description The AT52BR3224A(T) combines a 32-megabit Flash (2M x 16) and a 4-megabit SRAM (orga- nized as 256K x 16 stacked 66-ball CBGA package. The AT52BR3228A(T) combines a 32-megabit Flash (2M x 16) and an 8-megabit SRAM (organized as 512K x 16 stacked 66-ball CBGA package. The stacked modules operate at 2.7V to 3.3V in the industrial temper- ature range ...
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... It is not recommended that the six-byte code reside in the software of the final product but only exist in external programming code. AT52BR3224A(T)/3228A( 0.9V or above, normal program and erase opera- PP ...
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... Block Diagram OUTPUT BUFFER INPUT A0 - A20 BUFFER ADDRESS LATCH Y-DECODER X-DECODER 3338B–STKD–6/03 AT52BR3224A(T)/3228A(T) I/O0 - I/O15 INPUT BUFFER IDENTIFIER REGISTER STATUS REGISTER COMMAND REGISTER DATA COMPARATOR WRITE STATE MACHINE Y-GATING MAIN MEMORY RESET RDY/BUSY PROGRAM/ERASE VPP VOLTAGE SWITCH VCC ...
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... WORD PROGRAMMING: Once a memory block is erased programmed (to a logical “0” word-by-word basis. Programming is accomplished via the internal device command reg- ister and is a four-bus cycle operation. The device will automatically generate the required internal program pulses. AT52BR3224A(T)/3228A( ...
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... Once I/O7 has gone high, status information on the other pins can be checked. The Data Polling status bit must be used in conjunction with the erase/program and V bit as shown in the algorithm in Figures 1 and 2 on page 11. 3338B–STKD–6/03 AT52BR3224A(T)/3228A(T) voltage is less that 0.4V. When V PP cycle ...
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... I/O0 is low, the sector can be programmed; if the data on I/O0 is high, the program lockdown feature has been enabled and the sector cannot be programmed. The software product identification exit code should be used to return to standard operation. AT52BR3224A(T)/3228A(T) 8 status bit has been set to a “1”, the system must write the ...
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... Product ID Entry command is given followed by a normal read operation from an address within the protection register. After determining whether block B is protected or not, or reading the protection register, the Product ID Exit command must be given prior to performing any other operation. 3338B–STKD–6/03 AT52BR3224A(T)/3228A(T) 9 ...
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... CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from OUTPUT LEVELS: For the device, output high levels (V For 2.7V - 3.6V output levels, V must be regulated to 2.0V ± 10%, while V power). AT52BR3224A(T)/3228A(T) 10 power-on delay: once less than V . (e) V ...
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... I/O7 should be rechecked even if I/O5 = “1” because I/O7 may change simultaneously with I/O5. 3338B–STKD–6/03 Figure 2. Data Polling Algorithm (Configuration Register = 01) YES YES Program/Erase Operation Successful, Device in Read Mode Note: AT52BR3224A(T)/3228A(T) START Read I/O7 - I/O0 Read I/O7 - I/O0 NO Toggle Bit = Toggle? YES NO I/O3, I/ YES Read I/O7 - I/O0 Twice Toggle Bit = ...
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... Operation Not Successful, Write Product ID Exit Command Note: 1. The system should recheck the toggle bit even if I/O5 = “1” because the toggle bit may stop toggling as I/O5 changes to “1”. AT52BR3224A(T)/3228A(T) 12 Figure 4. Toggle Bit Algorithm (Configuration Register = 01) NO Program/Erase Operation Successful Note: 1 ...
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... I/O3 switches to a “1” when the V 3338B–STKD–6/03 I/O7 I/ 00/01 0 TOGGLE 0 0 TOGGLE DATA DATA 0 TOGGLE level is not high enough to successfully perform program and erase operations. PP AT52BR3224A(T)/3228A(T) Status Bit (1) (2) I/O5 I/O3 I/O2 00/01 00/01 00/ TOGGLE 0 0 TOGGLE DATA DATA DATA ...
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... Temperature under Bias................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C All Input Voltages (including NC Pins) with Respect to Ground .................................. -0.6V to +6.25V All Output Voltages with Respect to Ground ............................ -0. Voltage with Respect to Ground .................................. -0.6V to +13.0V AT52BR3224A(T)/3228A(T) 14 (1) 2nd Bus 3rd Bus Cycle Cycle Data Addr Data ...
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... All address lines not specified in the above table must be “0” when accessing the protection register, i.e., A20 - 3338B–STKD–6/03 Block AT52BR3224A(T)/3228A( ...
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... SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 AT52BR3224A(T)/3228A(T) 16 x16 Address Range (A20 - A0) 00000 - 00FFF 01000 - 01FFF 02000 - 02FFF 03000 - 03FFF 04000 - 04FFF 05000 - 05FFF 06000 - 06FFF 07000 - 07FFF 08000 - 0FFFF 10000 - 17FFF 18000 - 1FFFF ...
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... SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 3338B–STKD–6/03 AT52BR3224A(T)/3228A(T) x16 Address Range (A20 - A0) F0000 - F7FFF F8000 - FFFFF 100000 - 107FFF 108000 - 10FFFF 110000 - 117FFF 118000 - 11FFFF 120000 - 127FFF 128000 - 12FFFF 130000 - 137FFF 138000 - 13FFFF ...
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... SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 AT52BR3224A(T)/3228A(T) 18 x16 Address Range (A20 - A0) 00000 - 07FFF 08000 - 0FFFF 10000 - 17FFF 18000 - 1FFFF 20000 - 27FFF 28000 - 2FFFF 30000 - 37FFF 38000 - 3FFFF 40000 - 47FFF 48000 - 4FFFF 50000 - 57FFF ...
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... SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 3338B–STKD–6/03 AT52BR3224A(T)/3228A(T) x16 Address Range (A20 - A0) 128000 - 12FFFF 130000 - 137FFF 138000 - 13FFFF 140000 - 147FFF 148000 - 14FFFF 150000 - 157FFF 158000 - 15FFFF 160000 - 167FFF 168000 - 16FFFF 170000 - 177FFF ...
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... H 4. Manufacturer Code: 001FH (x16), Device Code: 00C8H (x16)-Bottom Boot; 00C9H (x16)-Top Boot. 5. See details under “Software Product Identification Entry/Exit” on page 27 (min) = 0.9V; V (max) = 3.6V. IHPP IHPP 7. V (max) = 0.4V. ILPP AT52BR3224A(T)/3228A( RESET ...
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... Output Low Voltage OL1 V Output Low Voltage OL2 V Output High Voltage OH1 V Output High Voltage OH2 Note the erase mode mA. CC 3338B–STKD–6/03 AT52BR3224A(T)/3228A(T) Condition I 0. MHz OUT ...
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... Notes may be delayed may be delayed without impact ACC specified from OE or CE, whichever occurs first ( pF This parameter is characterized and is not 100% tested. AT52BR3224A(T)/3228A(T) 22 tRC ADDRESS VALID tCE tOE tACC tRO HIGH after the address transition without impact on t ...
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... Input Test Waveforms and Measurement Level Output Test Load Pin Capacitance ( MHz 25°C Symbol Typ OUT Note: This parameter is characterized and is not 100% tested. 3338B–STKD–6/03 AT52BR3224A(T)/3228A( < Max 6 12 Units Conditions ...
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... Chip Select Hold Time CH t Write Pulse Width ( Data Setup Time Data, OE Hold Time DH OEH t Write Pulse Width High WPH AC Word Load Waveforms WE Controlled CE Controlled AT52BR3224A(T)/3228A(T) 24 Min Max Units ...
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... ( WPH 555 AAA 555 555 WORD 0 WORD 1 WORD 2 WORD 3 AT52BR3224A(T)/3228A(T) Min Typ Max 500 80 0.3 1 555 INPUT AA DATA AAA Note Note 3 WORD 4 WORD 5 Units 150 µ ...
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... Toggle Bit Waveforms Notes: 1. Toggling either both OE and CE will operate toggle bit. The t input(s). 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. AT52BR3224A(T)/3228A(T) 26 (1) tOEH tOE HIGH Z An ...
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... Sector Lockdown Enable Algorithm (1)(6) LOAD DATA F0 TO ANY ADDRESS EXIT PRODUCT IDENTIFICATION (4) MODE Notes AT52BR3224A(T)/3228A(T) LOAD DATA AA TO ADDRESS 555 LOAD DATA 55 TO ADDRESS AAA LOAD DATA 80 TO ADDRESS 555 LOAD DATA AA TO ADDRESS 555 LOAD DATA 55 TO ADDRESS AAA ...
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... Features • Fully Static Operation and Tri-state Output • TTL Compatible Inputs and Outputs • Battery Backup – 1.2V (Min) Data Retention Voltage (V) 2.7 - 3.3 Block Diagram SCS1 SCS2 AT52BR3224A(T)/3228A(T) 28 Operation Current/I Speed (ns A17 SOE SLB SUB SWE Standby (mA) Current (µ ...
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... Supply Voltage CC V Ground SS V Input High Voltage IH (1) V Input Low Voltage IL Note: 1. Undershoot -1.5V for pulse width less than 30 ns. Undershoot is sampled, not 100% tested. IL 3338B–STKD–6/03 AT52BR3224A(T)/3228A(T) (1) Rating -0.3 to 3.6 -0.3 to 4.6 - -55 to 150 (2) (2) SLB SUB Mode X X Deselected H H ...
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... OH (1) Capacitance (Temp = 25° 1.0 MHz) Symbol Parameter C Input Capacitance (Add, SCS1, IN SCS2, SLB, SUB, SWE, SOE) C Output Capacitance (I/O) OUT Note: 1. These parameters are sampled and not 100% tested. AT52BR3224A(T)/3228A(T) 30 Test Condition V < V < < V < OUT ...
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... Input Rise and Fall Time Input and Output Timing Reference Level Output Load CLZ OLZ BLZ Others 3338B–STKD–6/ CHZ OHZ BHZ WHZ OW AT52BR3224A(T)/3228A( Min Max ...
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... AC Test Loads Note: AT52BR3224A(T)/3228A( OUT CL Including jig and scope capacitance 2.8V TM 1029 Ohm (1) 1728 Ohm 3338B–STKD–6/03 ...
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... ACS (3) t OLZ t (3) BLZ t (3) CLZ PREVIOUS DATA t ACS t (3) CLZ AT52BR3224A(T)/3228A( (3) t CHZ (3) t BHZ t (3) OHZ DATA VALID t OH DATA VALID t (3) CHZ DATA VALID 33 ...
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... Transition is measured ± 200 mV from steady state. This parameter is sampled and not 100% tested. 8. SCS1 in high for the standby, low for active SCS2 in low for the standby, high for active. SUB and SLB in high for the standby, low for active. AT52BR3224A(T)/3228A(T) 34 (1),(4),(8) ...
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... RC Data Retention Timing Diagram 1 VCC 2.7V IH VDR SCS1 VSS Data Retention Timing Diagram 2 VCC 2.7V SCS2 VDR 0.4V VSS 3338B–STKD–6/03 AT52BR3224A(T)/3228A(T) Test Condition SCS1 > 0. SCS2 < 0. SUB, SLB > 0. > 0. < 0.2V ...
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... Fully Static Operation and Tri-state Output • TTL Compatible Inputs and Outputs • Battery Backup – 1.2V (Min) Data Retention Voltage (V) 2.7 - 3.3 Block Diagram SCS1 SCS2 SOE SUB SWE AT52BR3224A(T)/3228A(T) 36 Operation Current/I Speed (ns A18 SLB Standby (mA) Current (µA) Temperature CC (Max) ...
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... Supply Voltage CC V Ground SS V Input High Voltage IH (1) V Input Low Voltage IL Note: 1. Undershoot -1.5V for pulse width less than 30 ns. Undershoot is sampled, not 100% tested. IL 3338B–STKD–6/03 AT52BR3224A(T)/3228A(T) (1) Rating -0.3 to 3.6 -0.3 to 4.6 - -55 to 150 (2) (2) SLB SUB Mode X X Deselected H H ...
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... OH (1) Capacitance (Temp = 25° 1.0 MHz) Symbol Parameter C Input Capacitance (Add, SCS1, IN SCS2, SLB, SUB, SWE, SOE) C Output Capacitance (I/O) OUT Note: 1. These parameters are sampled and not 100% tested. AT52BR3224A(T)/3228A(T) 38 Test Condition V < V < < V < OUT ...
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... Input Rise and Fall Time Input and Output Timing Reference Level Output Load CLZ OLZ BLZ Others 3338B–STKD–6/ CHZ OHZ BHZ WHZ OW AT52BR3224A(T)/3228A( Min Max ...
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... AC Test Loads Note: AT52BR3224A(T)/3228A( OUT CL Including jig and scope capacitance 2.8V TM 1029 Ohm (1) 1728 Ohm 3338B–STKD–6/03 ...
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... ACS (3) t OLZ t (3) BLZ t (3) CLZ PREVIOUS DATA t ACS t (3) CLZ AT52BR3224A(T)/3228A( (3) t CHZ (3) t BHZ t (3) OHZ DATA VALID t OH DATA VALID t (3) CHZ DATA VALID 41 ...
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... Transition is measured ± 200 mV from steady state. This parameter is sampled and not 100% tested. 8. SCS1 in high for the standby, low for active SCS2 in low for the standby, high for active. SUB and SLB in high for the standby, low for active. AT52BR3224A(T)/3228A(T) 42 (1),(4),(8) ...
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... RC Data Retention Timing Diagram 1 VCC 2.7V IH VDR SCS1 VSS Data Retention Timing Diagram 2 VCC 2.7V SCS2 VDR 0.4V VSS 3338B–STKD–6/03 AT52BR3224A(T)/3228A(T) Test Condition SCS1 > 0. SCS2 < 0. SUB, SLB > 0. > 0. < 0.2V ...
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... Ordering Information t (ns) Ordering Code ACC 70 AT52BR3224A-70CI 70 AT52BR3224AT-70CI 70 AT52BR3228A-70CI 70 AT52BR3228AT-70CI 66C5 66-ball, Plastic Chip-size Ball Grid Array Package (CBGA) AT52BR3224A(T)/3228A(T) 44 Flash Boot Block Flash Plane Architecture Bottom 32M – Single Bank Top 32M – Single Bank Bottom 32M – Single Bank Top 32M – ...
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... A1 Ball Corner e 1.20 REF Bottom View TITLE 66C5, 66-ball ( Array 1.2 mm Body, 0.8 mm Ball Pitch Chip-scale Ball Grid Array Package (CBGA) AT52BR3224A(T)/3228A(T) 0.12 C Seating Plane C Side View A1 A COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM E 9.90 10.00 10 ...
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem ...