AT52BR3224A-70CI ATMEL [ATMEL Corporation], AT52BR3224A-70CI Datasheet - Page 22
AT52BR3224A-70CI
Manufacturer Part Number
AT52BR3224A-70CI
Description
32-megabit Flash + 4-megabit/ 8-megabit SRAM Stack Memory
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT52BR3224A-70CI.pdf
(46 pages)
- Current page: 22 of 46
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AC Read Characteristics
AC Read Waveforms
Notes:
22
Symbol
t
t
t
t
t
t
t
RC
ACC
CE
OE
DF
OH
RO
(1)
(3)(4)
(2)
1. CE may be delayed up to t
2. OE may be delayed up to t
3. t
4. This parameter is characterized and is not 100% tested.
AT52BR3224A(T)/3228A(T)
without impact on t
DF
is specified from OE or CE, whichever occurs first (CL = 5 pF).
Parameter
Read Cycle Time
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
Output Hold from OE, CE or Address,
whichever occurred first
RESET to Output Delay
RESET
ACC
OUTPUT
ADDRESS
(1)(2)(3)(4)
OE
CE
.
ACC
CE
- t
- t
OE
CE
after the falling edge of CE without impact on t
after the address transition without impact on t
HIGH Z
tACC
tRO
ADDRESS VALID
tCE
tOE
tRC
OUTPUT
VALID
Min
tOH
0
0
0
32-Mbit Flash
tDF
CE
ACC
or by t
.
ACC
Max
100
70
70
70
40
25
- t
OE
after an address change
3338B–STKD–6/03
Units
ns
ns
ns
ns
ns
ns
ns
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